GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

baytrail: Configure MSR for 2-core and 4-core P-state configutation 

Suggested settings to try for performace regression:

2-core systems:
- MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL)
- MSR_POWER_MISC clear bit 2,3
- \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL)

4-core systems:
- MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL)
- MSR_POWER_MISC clear bit 2,3
- \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL)

BUG=chrome-os-partner:26211
BRANCH=baytrail
TEST=emerge-rambi chromeos-coreboot-rambi

Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/192573
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7213
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Duncan Laurie 2014-03-28 10:52:13 -07:00 committed by Marc Jones
parent 89f5292ee6
commit 31ac9e3a9a
2 changed files with 5 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/baytrail/acpi.c
View File

@ -354,8 +354,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
vid_min = pattrs->iacore_vids[IACORE_LFM]; vid_min = pattrs->iacore_vids[IACORE_LFM];
/* Set P-states coordination type based on MSR disable bit */ /* Set P-states coordination type based on MSR disable bit */
msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL;
coord_type = (msr.lo & SINGLE_PCTL) ? SW_ALL : HW_ALL;
/* Max Non-Turbo Frequency */ /* Max Non-Turbo Frequency */
clock_max = (ratio_max * pattrs->bclk_khz) / 1000; clock_max = (ratio_max * pattrs->bclk_khz) / 1000;

32
src/soc/intel/baytrail/cpu.c
View File

@ -68,37 +68,16 @@ const struct reg_script package_msr_script[] = {
/* Core level MSRs */ /* Core level MSRs */
const struct reg_script core_msr_script[] = { const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold */ /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
REG_MSR_RMW(MSR_POWER_MISC,
~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
/* Disable C1E */ /* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
REG_MSR_OR(MSR_POWER_MISC, 0x44), REG_MSR_OR(MSR_POWER_MISC, 0x44),
REG_SCRIPT_END REG_SCRIPT_END
}; };
/* Enable hardware coordination for 2-core, disable for 4-core */
static void baytrail_set_pstate_coord(void)
{
const struct pattrs *pattrs = pattrs_get();
msr_t pmg_cst = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
msr_t power_misc = rdmsr(MSR_POWER_MISC);
if (pattrs->num_cpus > 2) {
/* Disable hardware coordination */
pmg_cst.lo |= SINGLE_PCTL;
power_misc.lo &= ~(ENABLE_ULFM_AUTOCM_MASK |
ENABLE_INDP_AUTOCM_MASK);
} else {
/* Enable hardware coordination */
pmg_cst.lo &= ~SINGLE_PCTL;
power_misc.lo |= (ENABLE_ULFM_AUTOCM_MASK |
ENABLE_INDP_AUTOCM_MASK);
}
wrmsr(MSR_PMG_CST_CONFIG_CONTROL, pmg_cst);
wrmsr(MSR_POWER_MISC, power_misc);
}
void baytrail_init_cpus(device_t dev) void baytrail_init_cpus(device_t dev)
{ {
struct bus *cpu_bus = dev->link_list; struct bus *cpu_bus = dev->link_list;
@ -156,9 +135,6 @@ static void baytrail_core_init(device_t cpu)
/* Set core MSRs */ /* Set core MSRs */
reg_script_run(core_msr_script); reg_script_run(core_msr_script);
/* Set P-State coordination */
baytrail_set_pstate_coord();
/* Set this core to max frequency ratio */ /* Set this core to max frequency ratio */
set_max_freq(); set_max_freq();
} }