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baytrail: move cache-as-ram base address to 0xfe000000 

Moving the cache-as-ram base address to 0xfe000000 will
provide more breathing room in the physical address space.
It will also allow for larger SPI roms in the future.

BUG=chrome-os-partner:27045
BRANCH=baytrail
CQ-DEPEND=CL:*157278
TEST=Built and booted. Suspended and resumes. Vboot works, MRC
     settings are being saved as well.

Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/190700
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7212
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin 2014-03-19 11:48:33 -05:00 committed by Marc Jones
parent 565d409753
commit 89f5292ee6
1 changed files with 1 additions and 1 deletions
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src/soc/intel/baytrail/Kconfig
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@ -113,7 +113,7 @@ endif # HAVE_MRC
config DCACHE_RAM_BASE
hex
default 0xff800000
default 0xfe000000
config DCACHE_RAM_SIZE
hex