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skylake: Fix building without serial console 

In order to build without CONFIG_CONSOLE_SERIAL the Skylake
SOC Kconfig should not be enabling serial console by default.

Also fix other compile issues when serial console is disabled.

BUG=chrome-os-partner:40857
BRANCH=none
TEST=build glados without serial console enabled

Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55
Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/287438
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11043
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Duncan Laurie 2015-07-22 09:24:23 -07:00 committed by Patrick Georgi
parent efa615734e
commit 31be8e403f
3 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/skylake/Kconfig
View File

@ -17,8 +17,6 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select CACHE_ROM select CACHE_ROM
select CAR_MIGRATION select CAR_MIGRATION
select CONSOLE_SERIAL8250MEM
select CONSOLE_SERIAL8250MEM_32
select COLLECT_TIMESTAMPS select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_MICROCODE_IN_CBFS select CPU_MICROCODE_IN_CBFS

3
src/soc/intel/skylake/romstage/romstage.c
View File

@ -50,7 +50,8 @@ void soc_pre_console_init(struct romstage_params *params)
/* System Agent Early Initialization */ /* System Agent Early Initialization */
systemagent_early_init(); systemagent_early_init();
pch_uart_init(); if (IS_ENABLED(CONFIG_CONSOLE_UART8250MEM_32))
pch_uart_init();
} }
/* SOC initialization before RAM is enabled */ /* SOC initialization before RAM is enabled */

3
src/soc/intel/skylake/uart.c
View File

@ -36,7 +36,8 @@ static void pch_uart_read_resources(struct device *dev)
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Set the configured UART base address for the debug port */ /* Set the configured UART base address for the debug port */
if (pch_uart_is_debug(dev)) { if (IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32) &&
pch_uart_is_debug(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
res->size = 0x1000; res->size = 0x1000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |