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mb/google/brya: Update state of BB_RT_FORCE_PWR gpios 

This GPIO is used to force the USB retimers on Type-C ports to stay in a
powered state and can be used e.g., during a firmware update to the
retimer to force power on even when no device may be connected to the
port. However, its power rail is controlled elsewhere and coreboot is
not applying a FW update, so this GPIO should be driven low instead.

BUG=b:193402306
TEST=compile

Change-Id: I976a0b8252b31aacef476d5ee4bcf6b1ef2e79de
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Tim Wawrzynczak 2021-09-14 14:26:46 -06:00 committed by Felix Held
parent 683b294d3f
commit 31c96fe509
2 changed files with 2 additions and 2 deletions
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2
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
View File

@ -167,7 +167,7 @@ static const struct pad_config gpio_table[] = {
/* E3 : PROC_GP0 ==> TP94644 */ /* E3 : PROC_GP0 ==> TP94644 */
PAD_NC(GPP_E3, NONE), PAD_NC(GPP_E3, NONE),
/* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
PAD_CFG_GPO(GPP_E4, 1, DEEP), PAD_CFG_GPO(GPP_E4, 0, DEEP),
/* E5 : SATA_DEVSLP1 ==> NC */ /* E5 : SATA_DEVSLP1 ==> NC */
PAD_NC(GPP_E5, NONE), PAD_NC(GPP_E5, NONE),
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */

2
src/mainboard/google/brya/variants/baseboard/brya/gpio.c
View File

@ -167,7 +167,7 @@ static const struct pad_config gpio_table[] = {
/* E3 : PROC_GP0 ==> HPS_INT_ODL */ /* E3 : PROC_GP0 ==> HPS_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE),
/* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
PAD_CFG_GPO(GPP_E4, 1, DEEP), PAD_CFG_GPO(GPP_E4, 0, DEEP),
/* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
PAD_CFG_GPO(GPP_E5, 1, DEEP), PAD_CFG_GPO(GPP_E5, 1, DEEP),
/* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */