GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Enable full ROM access on AMD CS5530(A) (needed for CBFS). 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2009-10-07 14:36:16 +00:00
parent fdfaada706
commit 31f81a6de1
12 changed files with 77 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/advantech/pcm-5820/auto.c
View File

@ -31,6 +31,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
@ -40,6 +41,7 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
/* ram_check(0, 640 * 1024); */
}

2
src/mainboard/asi/mb_5blgp/auto.c
View File

@ -31,6 +31,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "cpu/x86/bist.h"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
@ -40,6 +41,7 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
/* ram_check(0, 640 * 1024); */
}

3
src/mainboard/asi/mb_5blmp/auto.c
View File

@ -32,6 +32,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc87351/pc87351_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
@ -45,6 +46,8 @@ static void main(unsigned long bist)
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();

2
src/mainboard/axus/tc320/auto.c
View File

@ -32,6 +32,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
@ -41,6 +42,7 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
/* ram_check(0, 640 * 1024); */
}

3
src/mainboard/bcom/winnet100/auto.c
View File

@ -32,6 +32,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
@ -45,6 +46,8 @@ static void main(unsigned long bist)
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();

3
src/mainboard/eaglelion/5bcm/auto.c
View File

@ -14,6 +14,7 @@
#include "superio/nsc/pc97317/pc97317_early_serial.c"
//#include "northbridge/intel/i440bx/raminit.h"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
@ -30,6 +31,8 @@ static void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
cs5530_enable_rom();
sdram_init();
/* Check all of memory */

3
src/mainboard/iei/juki-511p/auto.c
View File

@ -30,6 +30,7 @@
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83977f/w83977f_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
@ -51,6 +52,8 @@ static void main(unsigned long bist)
inb(0x043);
inb(0x843);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();

3
src/mainboard/iei/nova4899r/auto.c
View File

@ -30,6 +30,7 @@
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
#include "superio/winbond/w83977tf/w83977tf_early_serial.c"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
@ -46,6 +47,8 @@ static void main(unsigned long bist)
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();

3
src/mainboard/televideo/tc7020/auto.c
View File

@ -32,6 +32,7 @@
#include "northbridge/amd/gx1/raminit.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
@ -45,6 +46,8 @@ static void main(unsigned long bist)
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
cs5530_enable_rom();
/* Initialize RAM. */
sdram_init();

6
src/southbridge/amd/cs5530/cs5530.h
View File

@ -27,6 +27,12 @@ void cs5530_enable(device_t dev);
#endif
#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
#define ROM_WRITE_ENABLE (1 << 1)
#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
/* Selects PCI positive decoding for accesses to the configured ROM space. */
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)

47
src/southbridge/amd/cs5530/cs5530_enable_rom.c Normal file
View File

@ -0,0 +1,47 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include "cs5530.h"
static void cs5530_enable_rom(void)
{
uint8_t reg8;
/* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */
device_t dev = PCI_DEV(0, 0x12, 0);
/*
* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
*
* Make the ROM write-protected.
*/
reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG);
reg8 |= LOWER_ROM_ADDRESS_RANGE;
reg8 |= UPPER_ROM_ADDRESS_RANGE;
reg8 &= ~ROM_WRITE_ENABLE;
pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
/* Set positive decode on ROM. */
reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
reg8 |= BIOS_ROM_POSITIVE_DECODE;
pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
}

8
src/southbridge/amd/cs5530/cs5530_isa.c
View File

@ -45,14 +45,6 @@ static void cs5530_read_resources(device_t dev)
static void isa_init(struct device *dev)
{
uint8_t reg8;
// TODO: Test if needed, otherwise drop.
/* Set positive decode on ROM. */
reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
reg8 |= BIOS_ROM_POSITIVE_DECODE;
pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
}
static void cs5530_pci_dev_enable_resources(device_t dev)