Fixes to the smbus code. Now for the fun.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
c18170b241
commit
320c6a0102
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@ -1,114 +1,222 @@
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#define SMBUS_IO_BASE 0x5000
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#define SMBGSTATUS 0xe0
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#define SMBGCTL 0xe2
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#define SMBHSTADDR 0xe4
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#define SMBHSTDAT 0xe6
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#define SMBHSTCMD 0xe8
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#define SMBHSTFIFO 0xe9
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#define SMBHSTSTAT 0x0
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#define SMBSLVSTAT 0x1
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBSLVCTL 0x8
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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/* Define register settings */
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#define HOST_RESET 0xff
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#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
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#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
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#define SMBUS_TIMEOUT (100*1000*10)
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static void enable_smbus(void)
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{
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device_t dev;
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/* Power management controller */
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dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
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unsigned char c;
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/* Power management controller */
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dev = pci_locate_device(PCI_ID(0x1106,0x8235), 0);
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if (dev == PCI_DEV_INVALID) {
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die("SMBUS controller not found\r\n");
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}
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if (dev == PCI_DEV_INVALID) {
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die("SMBUS controller not found\r\n");
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}
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// set IO base address to SMBUS_IO_BASE
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pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
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// set IO base address to SMBUS_IO_BASE
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pci_write_config32(dev, 0x90, SMBUS_IO_BASE|1);
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// Enable SMBus
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pci_write_config8(dev, 0xd2, 0x01);
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// Enable SMBus
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c = pci_read_config8(dev, 0xd2);
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c |= 5;
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pci_write_config8(dev, 0xd2, c);
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c = pci_read_config8(dev, 0x54);
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c &= ~0x80;
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pci_write_config8(dev, 0xd2, c);
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print_debug("SMBus controller enabled\r\n");
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print_debug("SMBus controller enabled\r\n");
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}
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static inline void smbus_delay(void)
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{
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outb(0x80, 0x80);
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outb(0x80, 0x80);
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}
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static int smbus_wait_until_ready(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned short val;
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smbus_delay();
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val = inw(SMBUS_IO_BASE + SMBGSTATUS);
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if ((val & 0x800) == 0) {
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break;
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}
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} while(--loops);
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return loops?0:-1;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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c = my_inb(smbus_io_base + SMBHSTSTAT);
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while((c & 1) == 1) {
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printk_err("c is 0x%x\n", c);
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c = my_inb(smbus_io_base + SMBHSTSTAT);
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/* nop */
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}
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} while(--loops);
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return loops?0:-1;
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}
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void smbus_reset(void)
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{
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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my_outb(HOST_RESET, smbus_io_base + SMBHSTSTAT);
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smbus_wait_until_ready();
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printk_err("After reset status %#x\n", my_inb(smbus_io_base + SMBHSTSTAT));
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}
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static int smbus_wait_until_done(void)
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{
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned short val;
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smbus_delay();
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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do {
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unsigned char val;
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smbus_delay();
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val = inw(SMBUS_IO_BASE + SMBGSTATUS);
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if (((val & 0x8) == 0) | ((val & 0x437) != 0)) {
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break;
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}
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} while(--loops);
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return loops?0:-1;
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byte = my_inb(smbus_io_base + SMBHSTSTAT);
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if (byte & 1)
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break;
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} while(--loops);
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return loops?0:-1;
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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static void smbus_print_error(unsigned char host_status_register)
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{
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unsigned char global_control_register;
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unsigned char global_status_register;
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unsigned char byte;
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if (smbus_wait_until_ready() < 0) {
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return -1;
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}
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/* setup transaction */
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/* disable interrupts */
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outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), SMBUS_IO_BASE + SMBGCTL);
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/* set the device I'm talking too */
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outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
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/* set the command/address... */
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outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
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/* set up for a byte data read */
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outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x2), SMBUS_IO_BASE + SMBGCTL);
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/* clear any lingering errors, so the transaction will run */
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/* Do I need to write the bits to a 1 to clear an error? */
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outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
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/* clear the data word...*/
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outw(0, SMBUS_IO_BASE + SMBHSTDAT);
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/* start the command */
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outw((inw(SMBUS_IO_BASE + SMBGCTL) | (1 << 3)), SMBUS_IO_BASE + SMBGCTL);
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/* poll for transaction completion */
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if (smbus_wait_until_done() < 0) {
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return -1;
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}
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global_status_register = inw(SMBUS_IO_BASE + SMBGSTATUS);
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/* read results of transaction */
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byte = inw(SMBUS_IO_BASE + SMBHSTDAT) & 0xff;
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if (global_status_register != (1 << 4)) {
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return -1;
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}
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return byte;
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printk_err("smbus_error: 0x%02x\n", host_status_register);
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if (host_status_register & (1 << 4)) {
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printk_err("Interrup/SMI# was Failed Bus Transaction\n");
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}
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if (host_status_register & (1 << 3)) {
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printk_err("Bus Error\n");
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}
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if (host_status_register & (1 << 2)) {
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printk_err("Device Error\n");
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}
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if (host_status_register & (1 << 1)) {
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printk_err("Interrupt/SMI# was Successful Completion\n");
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}
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if (host_status_register & (1 << 0)) {
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printk_err("Host Busy\n");
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}
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}
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/* SMBus routines borrowed from VIA's Trident Driver */
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/* this works, so I am not going to touch it for now -- rgm */
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static unsigned char smbus_read(unsigned char devAdr, unsigned char bIndex,
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unsigned char *result)
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{
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unsigned short i;
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unsigned char bData;
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unsigned char sts;
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/* clear host status */
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my_outb(0xff, smbus_io_base);
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/* check SMBUS ready */
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for ( i = 0; i < 0xFFFF; i++ )
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if ( (my_inb(smbus_io_base) & 0x01) == 0 )
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break;
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/* set host command */
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my_outb(bIndex, smbus_io_base+3);
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/* set slave address */
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my_outb(devAdr | 0x01, smbus_io_base+4);
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/* start */
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my_outb(0x48, smbus_io_base+2);
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/* SMBUS Wait Ready */
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for ( i = 0; i < 0xFFFF; i++ )
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if ( ((sts = my_inb(smbus_io_base)) & 0x01) == 0 )
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break;
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if ((sts & ~3) != 0) {
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smbus_print_error(sts);
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return 0;
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}
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bData=my_inb(smbus_io_base+5);
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*result = bData;
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/* return 1 if ok */
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return 1;
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}
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/* for reference, here is the fancier version which we will use at some
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* point
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*/
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# if 0
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int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
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{
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unsigned char host_status_register;
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unsigned char byte;
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reset();
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smbus_wait_until_ready();
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/* setup transaction */
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/* disable interrupts */
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my_outb(my_inb(smbus_io_base + SMBHSTCTL) & (~1), smbus_io_base + SMBHSTCTL);
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/* set the device I'm talking too */
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my_outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBXMITADD);
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/* set the command/address... */
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my_outb(address & 0xFF, smbus_io_base + SMBHSTCMD);
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/* set up for a byte data read */
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my_outb((my_inb(smbus_io_base + SMBHSTCTL) & 0xE3) | (0x2 << 2),
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smbus_io_base + SMBHSTCTL);
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/* clear any lingering errors, so the transaction will run */
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my_outb(my_inb(smbus_io_base + SMBHSTSTAT), smbus_io_base + SMBHSTSTAT);
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/* clear the data byte...*/
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my_outb(0, smbus_io_base + SMBHSTDAT0);
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/* start the command */
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my_outb((my_inb(smbus_io_base + SMBHSTCTL) | 0x40),
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smbus_io_base + SMBHSTCTL);
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/* poll for transaction completion */
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smbus_wait_until_done();
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host_status_register = my_inb(smbus_io_base + SMBHSTSTAT);
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/* Ignore the In Use Status... */
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host_status_register &= ~(1 << 6);
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/* read results of transaction */
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byte = my_inb(smbus_io_base + SMBHSTDAT0);
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smbus_print_error(byte);
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*result = byte;
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return host_status_register != 0x02;
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}
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#endif
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