Rangeley: Fix incorrect BCLK
Not all Rangeley SKUs have a fixed 100MHz BCLK. As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0]. Using fixed BCLK was causing wrong values of core frequencies in _PSS table for SKUs that do not have BCLK=100MHz. Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f Signed-off-by: Hannah Williams <hannah.williams@dell.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -32,6 +32,7 @@ static int get_fsb_tsc(int *fsb, int *ratio)
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static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
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static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
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static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
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static const short rangeley_fsb[4] = { 83, 100, 133, 116 };
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msr_t msr;
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get_fms(&c, cpuid_eax(1));
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@ -56,10 +57,13 @@ static int get_fsb_tsc(int *fsb, int *ratio)
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case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
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case 0x3c: /* Haswell BCLK fixed at 100MHz */
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case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
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case 0x4d: /* Rangeley BCLK fixed at 100MHz */
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*fsb = 100;
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*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
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break;
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case 0x4d: /* Rangeley */
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*fsb = rangeley_fsb[rdmsr(MSR_FSB_FREQ).lo & 3];
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*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
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break;
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default:
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return -2;
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}
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@ -13,6 +13,7 @@
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*/
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#include <types.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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@ -20,6 +21,7 @@
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/intel/turbo.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include "model_406dx.h"
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@ -154,6 +156,20 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
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return (int)power;
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}
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static int get_core_frequency_mhz(int ratio)
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{
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int fsb, core_freq;
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/* Get BCLK - different SKUs can have different BCLK */
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fsb = get_timer_fsb();
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printk(BIOS_DEBUG, "BCLK:%d MHz ratio:%d\n", fsb, ratio);
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core_freq = DIV_ROUND_CLOSEST(fsb * ratio, 100) * 100;
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printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq);
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return core_freq;
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}
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static void generate_P_state_entries(int core, int cores_per_package)
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{
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int ratio_min, ratio_max, ratio_turbo, ratio_step;
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@ -177,7 +193,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* Max Non-Turbo Ratio */
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ratio_max = (msr.lo >> 8) & 0xff;
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}
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clock_max = ratio_max * RANGELEY_BCLK;
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clock_max = get_core_frequency_mhz(ratio_max);
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/* Calculate CPU TDP in mW */
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msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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@ -240,7 +256,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
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/* Calculate power at this ratio */
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power = calculate_power(power_max, ratio_max, ratio);
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clock = ratio * RANGELEY_BCLK;
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clock = get_core_frequency_mhz(ratio);
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acpigen_write_PSS_package(
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clock, /*MHz*/
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@ -15,8 +15,6 @@
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#ifndef _CPU_INTEL_MODEL_406DX_H
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#define _CPU_INTEL_MODEL_406DX_H
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/* Rangeley bus clock is fixed at 100MHz */
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#define RANGELEY_BCLK 100
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#define MSR_FEATURE_CONFIG 0x13c
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#define MSR_FLEX_RATIO 0x194
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