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Rangeley: Fix incorrect BCLK 

Not all Rangeley SKUs have a fixed 100MHz BCLK.

As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0].
Using fixed BCLK was causing wrong values of core frequencies in _PSS table
for SKUs that do not have BCLK=100MHz.

Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f
Signed-off-by: Hannah Williams <hannah.williams@dell.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2019-11-02 09:39:36 +02:00 committed by Patrick Georgi
parent 3042af6256
commit 32c8de10b0
3 changed files with 23 additions and 5 deletions
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6
src/cpu/intel/common/fsb.c
View File

@ -32,6 +32,7 @@ static int get_fsb_tsc(int *fsb, int *ratio)
static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
static const short rangeley_fsb[4] = { 83, 100, 133, 116 };
msr_t msr;
get_fms(&c, cpuid_eax(1));
@ -56,10 +57,13 @@ static int get_fsb_tsc(int *fsb, int *ratio)
case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
case 0x3c: /* Haswell BCLK fixed at 100MHz */
case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
case 0x4d: /* Rangeley BCLK fixed at 100MHz */
*fsb = 100;
*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
break;
case 0x4d: /* Rangeley */
*fsb = rangeley_fsb[rdmsr(MSR_FSB_FREQ).lo & 3];
*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
break;
default:
return -2;
}

20
src/cpu/intel/fsp_model_406dx/acpi.c
View File

@ -13,6 +13,7 @@
*/
#include <types.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
@ -20,6 +21,7 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include "model_406dx.h"
@ -154,6 +156,20 @@ static int calculate_power(int tdp, int p1_ratio, int ratio)
return (int)power;
}
static int get_core_frequency_mhz(int ratio)
{
int fsb, core_freq;
/* Get BCLK - different SKUs can have different BCLK */
fsb = get_timer_fsb();
printk(BIOS_DEBUG, "BCLK:%d MHz ratio:%d\n", fsb, ratio);
core_freq = DIV_ROUND_CLOSEST(fsb * ratio, 100) * 100;
printk(BIOS_DEBUG, "core frequency for ratio(%d) %dMHz\n", ratio, core_freq);
return core_freq;
}
static void generate_P_state_entries(int core, int cores_per_package)
{
int ratio_min, ratio_max, ratio_turbo, ratio_step;
@ -177,7 +193,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Max Non-Turbo Ratio */
ratio_max = (msr.lo >> 8) & 0xff;
}
clock_max = ratio_max * RANGELEY_BCLK;
clock_max = get_core_frequency_mhz(ratio_max);
/* Calculate CPU TDP in mW */
msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
@ -240,7 +256,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * RANGELEY_BCLK;
clock = get_core_frequency_mhz(ratio);
acpigen_write_PSS_package(
clock, /*MHz*/

2
src/cpu/intel/fsp_model_406dx/model_406dx.h
View File

@ -15,8 +15,6 @@
#ifndef _CPU_INTEL_MODEL_406DX_H
#define _CPU_INTEL_MODEL_406DX_H
/* Rangeley bus clock is fixed at 100MHz */
#define RANGELEY_BCLK 100
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194