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soc/intel/apollolake: Use ITSS common code 

This patch uses common ITSS library to setup
itss irq.

Change-Id: Id265505cfc106668aea25ad93e114fe20736b700
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19236
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Bora Guvendik 2017-04-10 15:49:02 -07:00 committed by Martin Roth
parent fcab4156c8
commit 33117ec601
6 changed files with 9 additions and 133 deletions
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1
src/soc/intel/apollolake/Kconfig
View File

@ -54,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_ACPI
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_PCR
select SOC_INTEL_COMMON_BLOCK_SA

3
src/soc/intel/apollolake/Makefile.inc
View File

@ -14,7 +14,6 @@ bootblock-y += car.c
bootblock-y += flash_ctrlr.c
bootblock-y += gpio.c
bootblock-y += heci.c
bootblock-y += itss.c
bootblock-y += lpc_lib.c
bootblock-y += mmap_boot.c
bootblock-y += pmutil.c
@ -29,7 +28,6 @@ romstage-y += flash_ctrlr.c
romstage-y += gpio.c
romstage-y += heci.c
romstage-y += i2c_early.c
romstage-y += itss.c
romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
romstage-y += lpc_lib.c
romstage-y += memmap.c
@ -60,7 +58,6 @@ ramstage-y += gpio.c
ramstage-y += graphics.c
ramstage-y += heci.c
ramstage-y += i2c.c
ramstage-y += itss.c
ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
ramstage-y += lpc.c
ramstage-y += lpc_lib.c

3
src/soc/intel/apollolake/chip.c
View File

@ -26,12 +26,13 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/itss.h>
#include <romstage_handoff.h>
#include <soc/iomap.h>
#include <soc/itss.h>
#include <soc/cpu.h>
#include <soc/flash_ctrlr.h>
#include <soc/intel/common/vbt.h>
#include <soc/itss.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <spi-generic.h>

2
src/soc/intel/apollolake/gpio.c
View File

@ -17,9 +17,9 @@
#include <assert.h>
#include <gpio.h>
#include <intelblocks/itss.h>
#include <intelblocks/pcr.h>
#include <soc/gpio.h>
#include <soc/itss.h>
#include <soc/pcr_ids.h>
#include <soc/pm.h>

13
src/soc/intel/apollolake/include/soc/itss.h
View File

@ -16,14 +16,11 @@
#ifndef _SOC_APOLLOLAKE_ITSS_H_
#define _SOC_APOLLOLAKE_ITSS_H_
#define GPIO_IRQ_START 50
#define GPIO_IRQ_END 119
#define GPIO_IRQ_START 50
#define GPIO_IRQ_END ITSS_MAX_IRQ
/* Set the interrupt polarity for provided IRQ to the APIC. */
void itss_set_irq_polarity(int irq, int active_low);
/* Snapshot and restore IRQ polarity settings for the inclusive range. */
void itss_snapshot_irq_polarities(int start, int end);
void itss_restore_irq_polarities(int start, int end);
#define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
#endif /* _SOC_APOLLOLAKE_ITSS_H_ */

120
src/soc/intel/apollolake/itss.c
View File

@ -1,120 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
* GNU General Public License for more details.
*/
#include <commonlib/helpers.h>
#include <console/console.h>
#include <intelblocks/pcr.h>
#include <stdint.h>
#include <soc/itss.h>
#include <soc/pcr_ids.h>
#define ITSS_MAX_IRQ 119
#define IRQS_PER_IPC 32
#define NUM_IPC_REGS ((ITSS_MAX_IRQ + IRQS_PER_IPC - 1)/IRQS_PER_IPC)
#define PCR_IPC0_CONF 0x3200
void itss_set_irq_polarity(int irq, int active_low)
{
uint32_t mask;
uint16_t reg;
const uint16_t port = PID_ITSS;
if (irq < 0 || irq > ITSS_MAX_IRQ)
return;
reg = PCR_IPC0_CONF + sizeof(uint32_t) * (irq / IRQS_PER_IPC);
mask = 1 << (irq % IRQS_PER_IPC);
pcr_rmw32(port, reg, ~mask, (active_low ? mask : 0));
}
static uint32_t irq_snapshot[NUM_IPC_REGS];
void itss_snapshot_irq_polarities(int start, int end)
{
int i;
int reg_start;
int reg_end;
const uint16_t port = PID_ITSS;
if (start < 0 || start > ITSS_MAX_IRQ ||
end < 0 || end > ITSS_MAX_IRQ || end < start)
return;
reg_start = start / IRQS_PER_IPC;
reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
for (i = reg_start; i < reg_end; i++) {
uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
irq_snapshot[i] = pcr_read32(port, reg);
}
}
static void show_irq_polarities(const char *msg)
{
int i;
const uint16_t port = PID_ITSS;
printk(BIOS_INFO, "ITSS IRQ Polarities %s:\n", msg);
for (i = 0; i < NUM_IPC_REGS; i++) {
uint16_t reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
printk(BIOS_INFO, "IPC%d: 0x%08x\n", i, pcr_read32(port, reg));
}
}
void itss_restore_irq_polarities(int start, int end)
{
int i;
int reg_start;
int reg_end;
const uint16_t port = PID_ITSS;
if (start < 0 || start > ITSS_MAX_IRQ ||
end < 0 || end > ITSS_MAX_IRQ || end < start)
return;
show_irq_polarities("Before");
reg_start = start / IRQS_PER_IPC;
reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
for (i = reg_start; i < reg_end; i++) {
uint32_t mask;
uint16_t reg;
int irq_start;
int irq_end;
irq_start = i * IRQS_PER_IPC;
irq_end = MIN(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
if (start > irq_end)
continue;
if (end < irq_start)
break;
/* Track bits within the bounds of of the register. */
irq_start = MAX(start, irq_start) % IRQS_PER_IPC;
irq_end = MIN(end, irq_end) % IRQS_PER_IPC;
/* Create bitmask of the inclusive range of start and end. */
mask = (((1U << irq_end) - 1) | (1U << irq_end));
mask &= ~((1U << irq_start) - 1);
reg = PCR_IPC0_CONF + sizeof(uint32_t) * i;
pcr_rmw32(port, reg, ~mask, (mask & irq_snapshot[i]));
}
show_irq_polarities("After");
}