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soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common config 

For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not
be selected.

Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This commit is contained in:
Johnny Lin 2023-01-16 11:42:35 +08:00 committed by David Hendricks
parent 80b1fa3332
commit 337f8a1733
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/xeon_sp/Kconfig
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@ -11,6 +11,7 @@ config SOC_INTEL_SKYLAKE_SP
bool
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_0
select NO_FSP_TEMP_RAM_EXIT
help
Intel Skylake-SP support
@ -19,6 +20,7 @@ config SOC_INTEL_COOPERLAKE_SP
select XEON_SP_COMMON_BASE
select PLATFORM_USES_FSP2_2
select CACHE_MRC_SETTINGS
select NO_FSP_TEMP_RAM_EXIT
help
Intel Cooper Lake-SP support
@ -38,7 +40,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER
select INTEL_CAR_NEM # For postcar only now
select INTEL_DESCRIPTOR_MODE_CAPABLE
select NO_FSP_TEMP_RAM_EXIT
select PARALLEL_MP_AP_WORK
select PMC_GLOBAL_RESET_ENABLE_LOCK
select POSTCAR_STAGE