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soc/intel/cannonlake: Correct ITSS port id. 

According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.

BUG=None
TEST=None

Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
This commit is contained in:
praveen hodagatta pranesh 2018-09-21 04:24:16 +08:00 committed by Subrata Banik
parent c423d7d8f1
commit 338c8002d2
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/cannonlake/include/soc/pcr_ids.h
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@ -35,7 +35,7 @@
#define PID_PSF4 0xbd #define PID_PSF4 0xbd
#define PID_SCS 0xc0 #define PID_SCS 0xc0
#define PID_RTC 0xc3 #define PID_RTC 0xc3
#define PID_ITSS 0xc2 #define PID_ITSS 0xc4
#define PID_LPC 0xc7 #define PID_LPC 0xc7
#define PID_SERIALIO 0xcb #define PID_SERIALIO 0xcb