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soc/intel/cannonlake: Fix memory corruptions

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Coverity detects source memory is overrun. Fix this issue by using
the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption.

Found-by: Coverity CID 1429762 1429774
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
John Zhao 2020-10-16 10:09:35 -07:00 committed by Patrick Georgi
parent b37d4b95d3
commit 33f234e356
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/cannonlake/fsp_params.c
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@ -355,14 +355,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpAdvancedErrorReporting,
config->PcieRpAdvancedErrorReporting,
sizeof(params->PcieRpAdvancedErrorReporting));
sizeof(config->PcieRpAdvancedErrorReporting));
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
sizeof(config->PcieRpSlotImplemented));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));
sizeof(config->PcieRpHotPlug));
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];