southbridge/intel/bd82x6x: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Ie709e5d232c474b41f2ea73d3785a7975d6604ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -23,6 +23,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216
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config SOUTH_BRIDGE_OPTIONS # dummy
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config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select SOUTHBRIDGE_INTEL_COMMON
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select SOUTHBRIDGE_INTEL_COMMON
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select IOAPIC
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select IOAPIC
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select HAVE_HARD_RESET
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select HAVE_HARD_RESET
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@ -17,6 +17,8 @@
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#ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
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#ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
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#define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
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#define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
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#include <arch/acpi.h>
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/* PCH types */
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/* PCH types */
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#define PCH_TYPE_CPT 0x1c /* CougarPoint */
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#define PCH_TYPE_CPT 0x1c /* CougarPoint */
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#define PCH_TYPE_PPT 0x1e /* IvyBridge */
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#define PCH_TYPE_PPT 0x1e /* IvyBridge */
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@ -479,13 +481,6 @@ early_usb_init (const struct southbridge_usb_port *portmap);
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#define GBL_EN (1 << 5)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define SCI_EN (1 << 0)
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@ -361,8 +361,8 @@ static void xhci_sleep(u8 slp_typ)
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u16 reg16;
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u16 reg16;
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switch (slp_typ) {
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switch (slp_typ) {
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case SLP_TYP_S3:
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case ACPI_S3:
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case SLP_TYP_S4:
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case ACPI_S4:
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reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
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reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
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reg16 &= ~0x03UL;
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reg16 &= ~0x03UL;
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pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
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pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
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@ -392,7 +392,7 @@ static void xhci_sleep(u8 slp_typ)
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pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
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pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
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break;
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break;
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case SLP_TYP_S5:
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case ACPI_S5:
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reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
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reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
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reg16 |= ((1 << 8) | 0x03);
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reg16 |= ((1 << 8) | 0x03);
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pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
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pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
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@ -424,27 +424,27 @@ static void southbridge_smi_sleep(void)
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/* Figure out SLP_TYP */
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/* Figure out SLP_TYP */
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reg32 = inl(pmbase + PM1_CNT);
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reg32 = inl(pmbase + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = (reg32 >> 10) & 7;
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slp_typ = acpi_sleep_from_pm1(reg32);
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if (smm_get_gnvs()->xhci)
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if (smm_get_gnvs()->xhci)
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xhci_sleep(slp_typ);
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xhci_sleep(slp_typ);
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/* Do any mainboard sleep handling */
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/* Do any mainboard sleep handling */
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mainboard_smi_sleep(slp_typ-2);
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mainboard_smi_sleep(slp_typ);
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#if CONFIG_ELOG_GSMI
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#if CONFIG_ELOG_GSMI
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/* Log S3, S4, and S5 entry */
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/* Log S3, S4, and S5 entry */
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if (slp_typ >= 5)
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if (slp_typ >= ACPI_S3)
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elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
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elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
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#endif
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#endif
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/* Next, do the deed.
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/* Next, do the deed.
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*/
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*/
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switch (slp_typ) {
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switch (slp_typ) {
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case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
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case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
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case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
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case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
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case 5:
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case ACPI_S3:
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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/* Gate memory reset */
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/* Gate memory reset */
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@ -453,8 +453,8 @@ static void southbridge_smi_sleep(void)
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/* Invalidate the cache before going to S3 */
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/* Invalidate the cache before going to S3 */
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wbinvd();
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wbinvd();
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break;
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break;
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case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
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case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
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case 7:
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case ACPI_S5:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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outl(0, pmbase + GPE0_EN);
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outl(0, pmbase + GPE0_EN);
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@ -483,7 +483,7 @@ static void southbridge_smi_sleep(void)
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outl(reg32 | SLP_EN, pmbase + PM1_CNT);
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outl(reg32 | SLP_EN, pmbase + PM1_CNT);
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/* Make sure to stop executing code here for S3/S4/S5 */
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ > 1)
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if (slp_typ >= ACPI_S3)
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halt();
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halt();
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/* In most sleep states, the code flow of this function ends at
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/* In most sleep states, the code flow of this function ends at
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