Get rid of a few warnings:
1. Add some more prototypes to lib.h 2. Include console.h when not using romcc 3. Eliminate an unused function 4. Set a default for SSE2, since it is just for ramtest performance Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -4,6 +4,7 @@
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#if CONFIG_USE_PRINTK_IN_CAR == 0
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#if CONFIG_USE_PRINTK_IN_CAR == 0
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#include "console_print.c"
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#include "console_print.c"
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#else /* CONFIG_USE_PRINTK_IN_CAR == 1 */
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#else /* CONFIG_USE_PRINTK_IN_CAR == 1 */
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#include <console/console.h>
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#include "console_printk.c"
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#include "console_printk.c"
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#endif /* CONFIG_USE_PRINTK_IN_CAR */
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#endif /* CONFIG_USE_PRINTK_IN_CAR */
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@ -48,6 +48,7 @@ config SSE
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config SSE2
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config SSE2
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bool
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bool
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default n
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help
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help
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Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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streaming SIMD instructions. Some parts of coreboot can be built
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streaming SIMD instructions. Some parts of coreboot can be built
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@ -19,8 +19,15 @@
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/* This file is for "nuisance prototypes" that have no other home. */
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/* This file is for "nuisance prototypes" that have no other home. */
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#ifndef __LIB_H__
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#define __LIB_H__
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#ifndef __ROMCC__ /* romcc doesn't support prototypes. */
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#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */
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/* Defined in src/lib/clog2.c */
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/* Defined in src/lib/clog2.c */
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unsigned long log2(unsigned long x);
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unsigned long log2(unsigned long x);
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#endif
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/* Defined in src/lib/lzma.c */
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/* Defined in src/lib/lzma.c */
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unsigned long ulzma(unsigned char *src, unsigned char *dst);
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unsigned long ulzma(unsigned char *src, unsigned char *dst);
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@ -28,3 +35,18 @@ unsigned long ulzma(unsigned char *src, unsigned char *dst);
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/* Defined in src/arch/i386/boot/gdt.c */
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/* Defined in src/arch/i386/boot/gdt.c */
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void move_gdt(void);
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void move_gdt(void);
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/* Defined in src/lib/ramtest.c */
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void ram_check(unsigned long start, unsigned long stop);
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/* Defined in src/pc80/serial.c */
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void uart_init(void);
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/* Defined in romstage.c */
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#if defined(CONFIG_CPU_AMD_LX) && CONFIG_CPU_AMD_LX
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void cache_as_ram_main(void);
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#else
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
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#endif
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#endif /* __ROMCC__ */
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#endif /* __LIB_H__ */
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@ -1,3 +1,4 @@
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#include <lib.h> /* Prototypes */
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#ifndef RAMINIT_SYSINFO
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#ifndef RAMINIT_SYSINFO
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#define RAMINIT_SYSINFO 0
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#define RAMINIT_SYSINFO 0
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@ -12,14 +13,6 @@ static inline void print_debug_sdram_8(const char *strval, uint32_t val)
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#endif
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#endif
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}
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}
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void sdram_no_memory(void)
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{
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print_err("No memory!!\r\n");
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while(1) {
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hlt();
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}
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}
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/* Setup SDRAM */
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/* Setup SDRAM */
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#if RAMINIT_SYSINFO == 1
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#if RAMINIT_SYSINFO == 1
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void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
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void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo)
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@ -1,3 +1,5 @@
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#include <lib.h> /* Prototypes */
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static void write_phys(unsigned long addr, unsigned long value)
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static void write_phys(unsigned long addr, unsigned long value)
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{
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{
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// Assembler in lib/ is very ugly. But we properly guarded
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// Assembler in lib/ is very ugly. But we properly guarded
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@ -17,7 +17,6 @@
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#include "option_table.h"
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/mc146818rtc_early.c"
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#define post_code(x) outb(x, 0x80)
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#include "pc80/serial.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "arch/i386/lib/console.c"
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#include "lib/ramtest.c"
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#include "lib/ramtest.c"
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@ -1,3 +1,5 @@
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#include <lib.h> /* Prototypes */
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/* Base Address */
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/* Base Address */
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#ifndef CONFIG_TTYS0_BASE
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#ifndef CONFIG_TTYS0_BASE
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#define CONFIG_TTYS0_BASE 0x3f8
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#define CONFIG_TTYS0_BASE 0x3f8
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