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mb/intel/adlrvp: Configure GPIOs to enable DMIC 

The patch configures GPIO pins to enable DMIC.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
This commit is contained in:
Sridhar Siricilla 2020-11-05 21:36:39 +05:30 committed by Subrata Banik
parent f2de1e7e19
commit 344a1bd43c
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
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@ -224,17 +224,17 @@ static const struct pad_config gpio_table[] = {
/* SNDW1_DATA */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
/* SNDW2_CLK */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
/* SNDW2_DATA */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
/* SNDW3_CLK */
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2),
/* SNDW3_DATA */
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2),
/* SNDW4_CLK */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
/* SNDW4_DATA */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
/* SMB_CLK */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),