nb/intel/i945: Use DEBUG_RAM_SETUP

Avoid preprocessor here, also we never set loglevel
to value of >8 so the call would not be made.

The calls to ram_check() were removed, for a long
time that function has not tested start..stop region.

Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/mainboard/asus/p5gc-mx/romstage.c

@@ -220,9 +220,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 

src/mainboard/getac/p470/romstage.c

@@ -271,9 +271,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 

src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c

@@ -172,9 +172,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 

src/mainboard/ibase/mb899/romstage.c

@@ -231,9 +231,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 

src/mainboard/intel/d945gclf/romstage.c

@@ -151,9 +151,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
 

src/mainboard/kontron/986lcd-m/romstage.c

@@ -279,9 +279,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 

src/mainboard/lenovo/t60/romstage.c

@@ -208,9 +208,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 

src/mainboard/lenovo/x60/romstage.c

@@ -211,9 +211,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 

src/mainboard/lenovo/z61t/romstage.c

@@ -209,9 +209,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, spd_addrmap);
 

src/mainboard/roda/rk886ex/romstage.c

@@ -244,9 +244,8 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Enable SPD ROMs and DDR-II DRAM */
 	enable_smbus();
 
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	if (CONFIG(DEBUG_RAM_SETUP))
 		dump_spd_registers();
-#endif
 
 	sdram_initialize(s3resume ? 2 : 0, NULL);
 

src/northbridge/intel/i945/early_init.c

@@ -940,23 +940,9 @@ void i945_late_initialization(int s3resume)
 
 	i945_setup_root_complex_topology();
 
-#if !CONFIG(HAVE_ACPI_RESUME)
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
-#if CONFIG(DEBUG_RAM_SETUP)
+	if (CONFIG(DEBUG_RAM_SETUP))
 		sdram_dump_mchbar_registers();
 
-	{
-		/* This will not work if TSEG is in place! */
-		u32 tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
-
-		printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
-		ram_check(0x00000000, 0x000a0000);
-		ram_check(0x00100000, tom);
-	}
-#endif
-#endif
-#endif
-
 	MCHBAR16(SSKPD) = 0xCAFE;
 
 	i945_prepare_resume(s3resume);

src/northbridge/intel/i945/i945.h

@@ -375,6 +375,7 @@ void print_pci_devices(void);
 void dump_pci_device(unsigned int dev);
 void dump_pci_devices(void);
 void dump_spd_registers(void);
+void sdram_dump_mchbar_registers(void);
 
 u32 decode_igd_memory_size(u32 gms);
 u32 decode_tseg_size(const u8 esmramc);

src/northbridge/intel/i945/raminit.c

@@ -96,7 +96,6 @@ static void ram_read32(u32 offset)
 	read32((void *)offset);
 }
 
-#if CONFIG(DEBUG_RAM_SETUP)
 void sdram_dump_mchbar_registers(void)
 {
 	int i;
@@ -108,7 +107,6 @@ void sdram_dump_mchbar_registers(void)
 		printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
 	}
 }
-#endif
 
 static int memclk(void)
 {

src/northbridge/intel/i945/raminit.h

@@ -69,8 +69,4 @@ void receive_enable_adjust(struct sys_info *sysinfo);
 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
 int fixup_i945_errata(void);
 void udelay(u32 us);
-
-#if CONFIG(DEBUG_RAM_SETUP)
-void sdram_dump_mchbar_registers(void);
-#endif
 #endif				/* RAMINIT_H */