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AGESA: Remove duplicate OemCustomizeInitEarly declarations 

Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7158
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki 2014-10-21 13:43:46 +03:00
parent 4b5a71179a
commit 34ad72cd03
41 changed files with 35 additions and 276 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/amd/inagua/PlatformGnbPcie.c
View File

@ -20,6 +20,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

2
src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
View File

@ -64,6 +64,4 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

3
src/mainboard/amd/olivehill/PlatformGnbPcie.c
View File

@ -21,9 +21,10 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {

32
src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

3
src/mainboard/amd/parmer/PlatformGnbPcie.c
View File

@ -21,9 +21,10 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*

32
src/mainboard/amd/parmer/PlatformGnbPcieComplex.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/amd/persimmon/PlatformGnbPcie.c
View File

@ -20,6 +20,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

4
src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
View File

@ -65,9 +65,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/amd/south_station/PlatformGnbPcie.c
View File

@ -20,6 +20,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

4
src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
View File

@ -64,9 +64,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

3
src/mainboard/amd/thatcher/PlatformGnbPcie.c
View File

@ -21,9 +21,10 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
/*

32
src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/amd/torpedo/PlatformGnbPcie.c
View File

@ -20,6 +20,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE

4
src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h
View File

@ -64,9 +64,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/amd/union_station/PlatformGnbPcie.c
View File

@ -25,6 +25,7 @@
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

4
src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
View File

@ -64,9 +64,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/asrock/e350m1/PlatformGnbPcie.c
View File

@ -25,6 +25,7 @@
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

4
src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
View File

@ -64,9 +64,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

3
src/mainboard/asrock/imb-a180/PlatformGnbPcie.c
View File

@ -21,9 +21,10 @@
#include "amdlib.h"
#include "Ids.h"
#include "heapManager.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
static const PCIe_PORT_DESCRIPTOR PortList [] = {

32
src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h
View File

@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

5
src/mainboard/asus/f2a85-m/PlatformGnbPcie.c
View File

@ -17,8 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "PlatformGnbPcieComplex.h"
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE

31
src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h
View File

@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h>
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c
View File

@ -26,6 +26,7 @@
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
/*---------------------------------------------------------------------------------------*/
/**

4
src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h
View File

@ -66,9 +66,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

5
src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c
View File

@ -17,8 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "PlatformGnbPcieComplex.h"
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE

31
src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h
View File

@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h>
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
View File

@ -21,6 +21,7 @@
#include "PlatformGnbPcieComplex.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

2
src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
View File

@ -79,6 +79,4 @@
#define GNB_GPP_PORT8_CHANNEL_TYPE 4
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0
void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly);
#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */

5
src/mainboard/lenovo/g505s/PlatformGnbPcie.c
View File

@ -17,8 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "PlatformGnbPcieComplex.h"
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
#include <northbridge/amd/agesa/agesawrapper.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE

31
src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h
View File

@ -1,31 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
#include <vendorcode/amd/agesa/f15tn/AGESA.h>
#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h>
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c
View File

@ -25,6 +25,7 @@
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

4
src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h
View File

@ -65,9 +65,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

1
src/mainboard/lippert/toucan-af/PlatformGnbPcie.c
View File

@ -25,6 +25,7 @@
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE

4
src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h
View File

@ -65,9 +65,5 @@
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H

3
src/northbridge/amd/agesa/agesawrapper.h
View File

@ -65,4 +65,7 @@ void *agesawrapper_getlateinitptr (int pick);
AGESA_STATUS agesawrapper_fchs3earlyrestore(void);
AGESA_STATUS agesawrapper_fchs3laterestore(void);
void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly);
void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost);
#endif /* _AGESAWRAPPER_H_ */

2
src/northbridge/amd/agesa/family12/agesawrapper.c
View File

@ -47,8 +47,6 @@ VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
UINT32 ReadAmdSbPmr(IN UINT8 IndexValue, OUT UINT8 * DataValue);
UINT32 WriteAmdSbPmr(IN UINT8 IndexValue, IN UINT8 DataValue);

2
src/northbridge/amd/agesa/family14/agesawrapper.c
View File

@ -46,8 +46,6 @@ VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(VOID)
{
UINT64 MsrReg;

4
src/northbridge/amd/agesa/family15/agesawrapper.c
View File

@ -47,11 +47,11 @@ VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
/* TODO: Function body should be in mainboard directory. */
static VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS * InitEarly)
void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly)
{
}
static VOID OemCustomizeInitPost(AMD_POST_PARAMS *InitPost)
void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost)
{
#if IS_ENABLED(CONFIG_BOARD_AMD_DINAR)
InitPost->MemConfig.UmaMode = UMA_AUTO;

2
src/northbridge/amd/agesa/family15rl/agesawrapper.c
View File

@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
UINT64 MsrReg;

2
src/northbridge/amd/agesa/family15tn/agesawrapper.c
View File

@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
UINT64 MsrReg;

2
src/northbridge/amd/agesa/family16kb/agesawrapper.c
View File

@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
UINT64 MsrReg;