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AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper 

Split FCH parts to southbridge/hudson.

Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7159
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki 2014-10-20 08:49:16 +03:00
parent 88ff8b541f
commit 4b5a71179a
21 changed files with 541 additions and 3322 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/amd/olivehill/Makefile.inc
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@ -18,11 +18,9 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c

2
src/mainboard/amd/parmer/Makefile.inc
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@ -18,11 +18,9 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c

2
src/mainboard/amd/thatcher/Makefile.inc
View File

@ -18,11 +18,9 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c

2
src/mainboard/asrock/imb-a180/Makefile.inc
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@ -18,11 +18,9 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c

638
src/mainboard/asrock/imb-a180/agesawrapper.c
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@ -1,638 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include <stdint.h>
#include <string.h>
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "heapManager.h"
#include "FchPlatform.h"
#include "Fch.h"
#include <cpu/amd/agesa/s3_resume.h>
#include <arch/io.h>
#include <device/device.h>
#include "hudson.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
case PICK_IVRS:
return AcpiIvrs;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
"Alib:%x, AcpiIvrs:%x in %s\n",
(unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
(unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/asus/f2a85-m/Makefile.inc
View File

@ -18,11 +18,9 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c

636
src/mainboard/asus/f2a85-m/agesawrapper.c
View File

@ -1,636 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#include <arch/io.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <stdint.h>
#include <string.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
case PICK_IVRS:
return AcpiIvrs;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
"Alib:%x, AcpiIvrs:%x in %s\n",
(unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
(unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
#if 1 /* TODO: Get the param from Nv storage. */
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
#endif
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
#if 1 /* TODO:Get params from Volatile storage. */
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
#endif
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
#if 1 /* TODO: Save the params to NvStorage */
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
#endif
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
#if 1 /* TODO: Save the params to VolatileStorage */
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
#endif
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/asus/f2a85-m_le/Makefile.inc
View File

@ -18,11 +18,9 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c

1
src/mainboard/asus/f2a85-m_le/agesawrapper.c
View File

@ -1 +0,0 @@
#include "../f2a85-m/agesawrapper.c"

2
src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc
View File

@ -18,12 +18,10 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ramstage-y += ec.c

625
src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c
View File

@ -1,625 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
uint32_t agesawrapper_amdinitcpuio(void)
{
pci_devfn_t dev;
msr_t msr;
uint32_t reg32;
dev = PCI_DEV(0, 0x18, 1);
/* Enable legacy video routing: D18F1xF4 VGA Enable */
pci_io_write_config32(dev, 0xf4, 1);
/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
* Last address before processor local APIC at FEE00000
*/
pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7));
/* Lowest NP address is HPET at FED00000 */
pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3);
/* Map the remaining PCI hole as posted MMIO */
pci_io_write_config32(dev, 0x8C, 0x00fecf00);
msr = rdmsr(0xc001001a);
reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */
pci_io_write_config32(dev, 0x88, reg32);
/* Send all IO (0000-FFFF) to southbridge. */
pci_io_write_config32(dev, 0xc4, 0x0000f000);
pci_io_write_config32(dev, 0xc0, 0x00000003);
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
case PICK_IVRS:
return AcpiIvrs;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
"Alib:%x, AcpiIvrs:%x in %s\n",
(unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
(unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
//FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
//FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/mainboard/lenovo/g505s/Makefile.inc
View File

@ -18,12 +18,10 @@
#
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ramstage-y += ec.c

625
src/mainboard/lenovo/g505s/agesawrapper.c
View File

@ -1,625 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "PlatformGnbPcieComplex.h"
#define __SIMPLE_DEVICE__
#include <arch/io.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <device/device.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
#define FILECODE UNASSIGNED_FILE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
uint32_t agesawrapper_amdinitcpuio(void)
{
pci_devfn_t dev;
msr_t msr;
uint32_t reg32;
dev = PCI_DEV(0, 0x18, 1);
/* Enable legacy video routing: D18F1xF4 VGA Enable */
pci_io_write_config32(dev, 0xf4, 1);
/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
* Last address before processor local APIC at FEE00000
*/
pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7));
/* Lowest NP address is HPET at FED00000 */
pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3);
/* Map the remaining PCI hole as posted MMIO */
pci_io_write_config32(dev, 0x8C, 0x00fecf00);
msr = rdmsr(0xc001001a);
reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */
pci_io_write_config32(dev, 0x88, reg32);
/* Send all IO (0000-FFFF) to southbridge. */
pci_io_write_config32(dev, 0xc4, 0x0000f000);
pci_io_write_config32(dev, 0xc0, 0x00000003);
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
{
switch (pick) {
case PICK_DMI:
return DmiTable;
case PICK_PSTATE:
return AcpiPstate;
case PICK_SRAT:
return AcpiSrat;
case PICK_SLIT:
return AcpiSlit;
case PICK_WHEA_MCE:
return AcpiWheaMce;
case PICK_WHEA_CMC:
return AcpiWheaCmc;
case PICK_ALIB:
return AcpiAlib;
case PICK_IVRS:
return AcpiIvrs;
default:
return NULL;
}
}
AGESA_STATUS agesawrapper_amdinitmid(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
"Alib:%x, AcpiIvrs:%x in %s\n",
(unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat,
(unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc,
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
{
AGESA_STATUS Status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
//FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
return Status;
}
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
//FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
S3DataType = S3DataTypeNonVolatile;
printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
}
return Status;
}

2
src/northbridge/amd/agesa/family15rl/Makefile.inc
View File

@ -18,6 +18,8 @@
#
romstage-y += dimmSpd.c
romstage-y += agesawrapper.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
ramstage-y += agesawrapper.c

405
src/mainboard/amd/parmer/agesawrapper.c → src/northbridge/amd/agesa/family15rl/agesawrapper.c
View File

@ -30,7 +30,6 @@
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "heapManager.h"
#include "FchPlatform.h"
@ -40,30 +39,30 @@
#include <device/device.h>
#include "hudson.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@ -71,63 +70,61 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void)
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
@ -136,30 +133,24 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
@ -167,27 +158,24 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
@ -195,30 +183,26 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AmdCreateStruct(&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
return status;
}
@ -226,36 +210,30 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdCreateStruct(&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
VOID *agesawrapper_getlateinitptr(int pick)
{
switch (pick) {
case PICK_DMI:
@ -285,65 +263,59 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
@ -353,130 +325,91 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
return status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
{
AGESA_STATUS Status;
AGESA_STATUS status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
status = AmdLateRunApTask(&ApExeParams);
ASSERT(status == AGESA_SUCCESS);
return Status;
return status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
OemAgesaGetS3Info(S3DataType,
(u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
//FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdCreateStruct(&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
OemAgesaGetS3Info(S3DataType,
(u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
Status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
@ -485,67 +418,25 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
//FchParams = InitEnvCfgDefault;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
@ -557,10 +448,9 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info(S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
@ -569,43 +459,40 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
Status = OemAgesaSaveS3Info(S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
AmdReleaseStruct(&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
Status = AmdReadEventLog(&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n",
(unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n",
(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n",
(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog(&AmdEventParams);
}
return Status;

2
src/northbridge/amd/agesa/family15tn/Makefile.inc
View File

@ -18,6 +18,8 @@
#
romstage-y += dimmSpd.c
romstage-y += agesawrapper.c
ramstage-y += iommu.c
ramstage-y += northbridge.c
ramstage-y += agesawrapper.c

404
src/mainboard/amd/olivehill/agesawrapper.c → src/northbridge/amd/agesa/family15tn/agesawrapper.c
View File

@ -30,7 +30,6 @@
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "heapManager.h"
#include "FchPlatform.h"
@ -40,94 +39,92 @@
#include <device/device.h>
#include "hudson.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
@ -136,30 +133,24 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
@ -167,27 +158,24 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
@ -195,26 +183,23 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AmdCreateStruct(&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
@ -225,36 +210,30 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdCreateStruct(&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
VOID *agesawrapper_getlateinitptr(int pick)
{
switch (pick) {
case PICK_DMI:
@ -284,65 +263,59 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
@ -352,129 +325,91 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
return status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
{
AGESA_STATUS Status;
AGESA_STATUS status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
status = AmdLateRunApTask(&ApExeParams);
ASSERT(status == AGESA_SUCCESS);
return Status;
return status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
OemAgesaGetS3Info(S3DataType,
(u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdCreateStruct(&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
OemAgesaGetS3Info(S3DataType,
(u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
Status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
@ -483,66 +418,25 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
@ -554,10 +448,9 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
Status = OemAgesaSaveS3Info(S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
@ -566,43 +459,40 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
Status = OemAgesaSaveS3Info(S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
AmdReleaseStruct(&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
Status = AmdReadEventLog(&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n",
(unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n",
(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n",
(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog(&AmdEventParams);
}
return Status;

2
src/northbridge/amd/agesa/family16kb/Makefile.inc
View File

@ -18,5 +18,7 @@
#
romstage-y += dimmSpd.c
romstage-y += agesawrapper.c
ramstage-y += northbridge.c
ramstage-y += agesawrapper.c

413
src/mainboard/amd/thatcher/agesawrapper.c → src/northbridge/amd/agesa/family16kb/agesawrapper.c
View File

@ -30,7 +30,6 @@
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "PlatformGnbPcieComplex.h"
#include "Filecode.h"
#include "heapManager.h"
#include "FchPlatform.h"
@ -40,30 +39,30 @@
#include <device/device.h>
#include "hudson.h"
#define FILECODE UNASSIGNED_FILE_FILECODE
/* ACPI table pointers returned by AmdInitLate */
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *DmiTable = NULL;
VOID *AcpiPstate = NULL;
VOID *AcpiSrat = NULL;
VOID *AcpiSlit = NULL;
VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID *AcpiAlib = NULL;
VOID *AcpiIvrs = NULL;
VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly);
AGESA_STATUS agesawrapper_amdinitcpuio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@ -71,63 +70,61 @@ AGESA_STATUS agesawrapper_amdinitcpuio(void)
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitmmio(void)
{
AGESA_STATUS Status;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
UINT64 MsrReg;
AMD_CONFIG_PARAMS StdHeader;
/*
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
/*
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
*/
LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader);
MsrReg = MsrReg | 0x0000400000000000;
LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
Status = AGESA_SUCCESS;
return Status;
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_amdinitreset(void)
@ -136,30 +133,24 @@ AGESA_STATUS agesawrapper_amdinitreset(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESET_PARAMS AmdResetParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
LibAmdMemFill (&AmdResetParams,
0,
sizeof (AMD_RESET_PARAMS),
&(AmdResetParams.StdHeader));
LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
AmdParamStruct.AllocationMethod = ByHost;
AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
AmdParamStruct.NewStructPtr = &AmdResetParams;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdResetParams.HtConfig.Depth = 0;
status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
@ -167,27 +158,24 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly (AmdEarlyParamsPtr);
AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
OemCustomizeInitEarly(AmdEarlyParamsPtr);
status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
@ -195,26 +183,23 @@ AGESA_STATUS agesawrapper_amdinitearly(void)
AGESA_STATUS agesawrapper_amdinitpost(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_POST_PARAMS *PostParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdInitPost (PostParams);
AmdCreateStruct(&AmdParamStruct);
PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitPost(PostParams);
AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
/* Initialize heap space */
EmptyHeap();
@ -225,36 +210,30 @@ AGESA_STATUS agesawrapper_amdinitenv(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_ENV_PARAMS *EnvParam;
AMD_ENV_PARAMS *EnvParam;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
status = AmdCreateStruct (&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
status = AmdCreateStruct(&AmdParamStruct);
EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitEnv (EnvParam);
status = AmdInitEnv(EnvParam);
AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus);
/* Initialize Subordinate Bus Number and Secondary Bus Number
* In platform BIOS this address is allocated by PCI enumeration code
Modify D1F0x18
*/
*/
return status;
}
VOID *
agesawrapper_getlateinitptr (
int pick
)
VOID *agesawrapper_getlateinitptr(int pick)
{
switch (pick) {
case PICK_DMI:
@ -284,65 +263,59 @@ AGESA_STATUS agesawrapper_amdinitmid(void)
AMD_INTERFACE_PARAMS AmdParamStruct;
/* Enable MMIO on AMD CPU Address Map Controller */
agesawrapper_amdinitcpuio ();
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
AGESA_STATUS agesawrapper_amdinitlate(void)
{
AGESA_STATUS Status;
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_LATE_PARAMS *AmdLateParams;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
AmdParamStruct.AllocationMethod = PostMemDram;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
/* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */
AmdCreateStruct(&AmdParamStruct);
AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr;
Status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
status = AmdInitLate(AmdLateParams);
AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus);
ASSERT(status == AGESA_SUCCESS);
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
DmiTable = AmdLateParams->DmiTable;
AcpiPstate = AmdLateParams->AcpiPState;
AcpiSrat = AmdLateParams->AcpiSrat;
AcpiSlit = AmdLateParams->AcpiSlit;
AcpiWheaMce = AmdLateParams->AcpiWheaMce;
AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
AcpiAlib = AmdLateParams->AcpiAlib;
AcpiIvrs = AmdLateParams->AcpiIvrs;
printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x,"
"AcpiSlit:%x, Mce:%x, Cmc:%x,"
@ -352,133 +325,91 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
(unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__);
/* AmdReleaseStruct (&AmdParamStruct); */
return Status;
return status;
}
AGESA_STATUS agesawrapper_amdlaterunaptask (
UINT32 Func,
UINT32 Data,
VOID *ConfigPtr
)
AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr)
{
AGESA_STATUS Status;
AGESA_STATUS status;
AP_EXE_PARAMS ApExeParams;
LibAmdMemFill (&ApExeParams,
0,
sizeof (AP_EXE_PARAMS),
&(ApExeParams.StdHeader));
LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader));
ApExeParams.StdHeader.AltImageBasePtr = 0;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
ApExeParams.StdHeader.Func = 0;
ApExeParams.StdHeader.ImageBasePtr = 0;
ApExeParams.FunctionNumber = Func;
ApExeParams.RelatedDataBlock = ConfigPtr;
Status = AmdLateRunApTask (&ApExeParams);
ASSERT(Status == AGESA_SUCCESS);
status = AmdLateRunApTask(&ApExeParams);
ASSERT(status == AGESA_SUCCESS);
return Status;
return status;
}
AGESA_STATUS agesawrapper_amdinitresume(void)
{
AGESA_STATUS status;
AMD_INTERFACE_PARAMS AmdParamStruct;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
AMD_RESUME_PARAMS *AmdResumeParamsPtr;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdParamStruct,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdParamStruct.StdHeader));
LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader));
AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
AmdParamStruct.AllocationMethod = PreMemHeap;
AmdParamStruct.StdHeader.AltImageBasePtr = 0;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdParamStruct.StdHeader.Func = 0;
AmdParamStruct.StdHeader.ImageBasePtr = 0;
AmdCreateStruct (&AmdParamStruct);
AmdCreateStruct(&AmdParamStruct);
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeNonVolatile;
#if 1 /* TODO: Get the param from Nv storage. */
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage);
#endif
OemAgesaGetS3Info(S3DataType,
(u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize,
(void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage);
status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr);
status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr);
AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus);
AmdReleaseStruct (&AmdParamStruct);
AmdReleaseStruct(&AmdParamStruct);
return status;
}
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_fchs3earlyrestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return status;
}
#endif
AGESA_STATUS agesawrapper_amds3laterestore(void)
{
AGESA_STATUS Status;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
AMD_S3LATE_PARAMS AmdS3LateParams;
AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
S3_DATA_TYPE S3DataType;
agesawrapper_amdinitcpuio();
LibAmdMemFill (&AmdS3LateParams,
0,
sizeof (AMD_S3LATE_PARAMS),
&(AmdS3LateParams.StdHeader));
LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.AllocationMethod = ByHost;
AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdS3LateParamsPtr = &AmdS3LateParams;
AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS);
AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
AmdCreateStruct (&AmdInterfaceParams);
AmdCreateStruct(&AmdInterfaceParams);
AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
S3DataType = S3DataTypeVolatile;
#if 1 /* TODO:Get params from Volatile storage. */
OemAgesaGetS3Info (S3DataType,
(u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
#endif
OemAgesaGetS3Info(S3DataType,
(u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize,
(void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage);
Status = AmdS3LateRestore (AmdS3LateParamsPtr);
Status = AmdS3LateRestore(AmdS3LateParamsPtr);
AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus);
ASSERT(Status == AGESA_SUCCESS);
@ -487,66 +418,25 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
#ifndef __PRE_RAM__
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3laterestore(void)
{
AGESA_STATUS status = AGESA_SUCCESS;
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return status;
}
#endif
#ifndef __PRE_RAM__
AGESA_STATUS agesawrapper_amdS3Save(void)
{
AGESA_STATUS Status;
AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
AMD_INTERFACE_PARAMS AmdInterfaceParams;
S3_DATA_TYPE S3DataType;
LibAmdMemFill (&AmdInterfaceParams,
0,
sizeof (AMD_INTERFACE_PARAMS),
&(AmdInterfaceParams.StdHeader));
LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader));
AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdInterfaceParams.AllocationMethod = PostMemDram;
AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
AmdInterfaceParams.StdHeader.Func = 0;
AmdCreateStruct(&AmdInterfaceParams);
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
Status = AmdS3Save(AmdS3SaveParamsPtr);
@ -557,12 +447,11 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
#if 1 /* TODO: Save the params to NvStorage */
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
#endif
Status = OemAgesaSaveS3Info(S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.NvStorage);
printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n",
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
(unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
@ -570,46 +459,40 @@ AGESA_STATUS agesawrapper_amdS3Save(void)
if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) {
S3DataType = S3DataTypeVolatile;
#if 1 /* TODO: Save the params to VolatileStorage */
Status = OemAgesaSaveS3Info (
S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage
);
#endif
Status = OemAgesaSaveS3Info(S3DataType,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize,
AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage);
}
OemAgesaSaveMtrr();
AmdReleaseStruct (&AmdInterfaceParams);
AmdReleaseStruct(&AmdInterfaceParams);
return Status;
}
#endif /* #ifndef __PRE_RAM__ */
#endif /* #ifndef __PRE_RAM__ */
AGESA_STATUS agesawrapper_amdreadeventlog (
UINT8 HeapStatus
)
AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
{
AGESA_STATUS Status;
EVENT_PARAMS AmdEventParams;
LibAmdMemFill (&AmdEventParams,
0,
sizeof (EVENT_PARAMS),
&(AmdEventParams.StdHeader));
LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader));
AmdEventParams.StdHeader.AltImageBasePtr = 0;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout;
AmdEventParams.StdHeader.Func = 0;
AmdEventParams.StdHeader.ImageBasePtr = 0;
AmdEventParams.StdHeader.HeapStatus = HeapStatus;
Status = AmdReadEventLog (&AmdEventParams);
Status = AmdReadEventLog(&AmdEventParams);
while (AmdEventParams.EventClass != 0) {
printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog (&AmdEventParams);
printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n",
(unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo);
printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n",
(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2);
printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n",
(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4);
Status = AmdReadEventLog(&AmdEventParams);
}
return Status;

2
src/southbridge/amd/agesa/hudson/Makefile.inc
View File

@ -10,6 +10,8 @@ ramstage-y += pci.c
ramstage-y += pcie.c
ramstage-y += sd.c
ramstage-y += agesawrapper.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c

92
src/southbridge/amd/agesa/hudson/agesawrapper.c Normal file
View File

@ -0,0 +1,92 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include "cpuRegisters.h"
#include "cpuCacheInit.h"
#include "cpuApicUtilities.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "Dispatcher.h"
#include "cpuCacheInit.h"
#include "amdlib.h"
#include "Filecode.h"
#include "heapManager.h"
#include "FchPlatform.h"
#include "Fch.h"
#include <cpu/amd/agesa/s3_resume.h>
#include <arch/io.h>
#include <device/device.h>
#include "hudson.h"
extern UINT8 picr_data[0x54], intr_data[0x54];
AGESA_STATUS agesawrapper_fchs3earlyrestore (void)
{
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3EarlyRestore(&FchParams);
return AGESA_SUCCESS;
}
AGESA_STATUS agesawrapper_fchs3laterestore (void)
{
FCH_DATA_BLOCK FchParams;
AMD_CONFIG_PARAMS StdHeader;
UINT8 byte;
StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
StdHeader.AltImageBasePtr = 0;
StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
StdHeader.Func = 0;
StdHeader.ImageBasePtr = 0;
FchParams.StdHeader = &StdHeader;
s3_resume_init_data(&FchParams);
FchInitS3LateRestore(&FchParams);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
outb(picr_data[byte], 0xC01);
}
/* APIC IRQ routine */
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
outb(byte | 0x80, 0xC00);
outb(intr_data[byte], 0xC01);
}
return AGESA_SUCCESS;
}