soc/amd/picasso: Update CPU support
Change the Stoney Ridge ID to Picasso. Rename family 15h. Get the number of cores/threads from CPUID as all D18 registers are new. Change-Id: I44c45db637897f6caf320032c9f79a3a1ab4d6c9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_ROMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_INIT_SIPI
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select ACPI_AMD_HARDWARE_SLEEP_VALUES
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select ACPI_AMD_HARDWARE_SLEEP_VALUES
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select COLLECT_TIMESTAMPS_NO_TSC
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select COLLECT_TIMESTAMPS_NO_TSC
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select DRIVERS_I2C_DESIGNWARE
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select DRIVERS_I2C_DESIGNWARE
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@ -32,6 +32,7 @@
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#include <amdblocks/acpi.h>
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#include <amdblocks/acpi.h>
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#include <soc/acpi.h>
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/southbridge.h>
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#include <soc/southbridge.h>
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#include <soc/northbridge.h>
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#include <soc/northbridge.h>
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#include <soc/nvs.h>
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#include <soc/nvs.h>
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@ -238,10 +239,7 @@ void generate_cpu_entries(struct device *device)
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{
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{
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int cores, cpu;
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int cores, cpu;
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/* Picasso is single node, just report # of cores */
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cores = get_cpu_count();
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cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
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cores++; /* number of cores is CmpCap+1 */
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printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
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printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
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/* Generate BSP \_PR.P000 */
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/* Generate BSP \_PR.P000 */
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@ -2,7 +2,7 @@
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2015-2016 Intel Corp.
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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* Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -54,10 +54,9 @@ static void pre_mp_init(void)
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x86_mtrr_check();
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x86_mtrr_check();
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}
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}
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static int get_cpu_count(void)
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int get_cpu_count(void)
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{
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{
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return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK)
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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+ 1;
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}
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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@ -118,22 +117,22 @@ void picasso_init_cpus(struct device *dev)
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set_warm_reset_flag();
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set_warm_reset_flag();
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}
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}
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static void model_15_init(struct device *dev)
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static void model_17_init(struct device *dev)
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{
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{
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check_mca();
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check_mca();
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setup_lapic();
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setup_lapic();
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}
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}
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static struct device_operations cpu_dev_ops = {
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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.init = model_17_init,
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};
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};
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static struct cpu_device_id cpu_table[] = {
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x670f00 },
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{ X86_VENDOR_AMD, 0x810f81 },
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{ 0, 0 },
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{ 0, 0 },
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};
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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static const struct cpu_driver model_17 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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.id_table = cpu_table,
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};
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};
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@ -22,6 +22,7 @@
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#define SOC_EARLY_VMTRR_TEMPRAM 2
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#define SOC_EARLY_VMTRR_TEMPRAM 2
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void picasso_init_cpus(struct device *dev);
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void picasso_init_cpus(struct device *dev);
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int get_cpu_count(void);
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void check_mca(void);
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void check_mca(void);
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#endif /* __PICASSO_CPU_H__ */
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#endif /* __PICASSO_CPU_H__ */
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@ -73,10 +73,6 @@
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#define D18F1_VGAEN 0xf4
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#define D18F1_VGAEN 0xf4
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# define VGA_ADDR_ENABLE (1 << 0)
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# define VGA_ADDR_ENABLE (1 << 0)
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/* D18F5 */
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#define NB_CAPABILITIES2 0x84
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#define CMP_CAP_MASK 0xff
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void amd_initcpuio(void);
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void amd_initcpuio(void);
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void domain_enable_resources(struct device *dev);
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void domain_enable_resources(struct device *dev);
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