soc/amd/picasso: Update CPU support

Change the Stoney Ridge ID to Picasso.  Rename family 15h.  Get the
number of cores/threads from CPUID as all D18 registers are new.

Change-Id: I44c45db637897f6caf320032c9f79a3a1ab4d6c9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-07-16 15:18:00 -06:00 committed by Martin Roth
parent 0bd0806d2f
commit 34c30565b0
5 changed files with 11 additions and 16 deletions

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@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
select X86_AMD_INIT_SIPI
select ACPI_AMD_HARDWARE_SLEEP_VALUES select ACPI_AMD_HARDWARE_SLEEP_VALUES
select COLLECT_TIMESTAMPS_NO_TSC select COLLECT_TIMESTAMPS_NO_TSC
select DRIVERS_I2C_DESIGNWARE select DRIVERS_I2C_DESIGNWARE

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@ -32,6 +32,7 @@
#include <amdblocks/acpi.h> #include <amdblocks/acpi.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/cpu.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <soc/northbridge.h> #include <soc/northbridge.h>
#include <soc/nvs.h> #include <soc/nvs.h>
@ -238,10 +239,7 @@ void generate_cpu_entries(struct device *device)
{ {
int cores, cpu; int cores, cpu;
/* Picasso is single node, just report # of cores */ cores = get_cpu_count();
cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK;
cores++; /* number of cores is CmpCap+1 */
printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores);
/* Generate BSP \_PR.P000 */ /* Generate BSP \_PR.P000 */

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@ -2,7 +2,7 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2015-2016 Intel Corp. * Copyright (C) 2015-2016 Intel Corp.
* Copyright (C) 2017 Advanced Micro Devices, Inc. * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -54,10 +54,9 @@ static void pre_mp_init(void)
x86_mtrr_check(); x86_mtrr_check();
} }
static int get_cpu_count(void) int get_cpu_count(void)
{ {
return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) return 1 + (cpuid_ecx(0x80000008) & 0xff);
+ 1;
} }
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
@ -118,22 +117,22 @@ void picasso_init_cpus(struct device *dev)
set_warm_reset_flag(); set_warm_reset_flag();
} }
static void model_15_init(struct device *dev) static void model_17_init(struct device *dev)
{ {
check_mca(); check_mca();
setup_lapic(); setup_lapic();
} }
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {
.init = model_15_init, .init = model_17_init,
}; };
static struct cpu_device_id cpu_table[] = { static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x670f00 }, { X86_VENDOR_AMD, 0x810f81 },
{ 0, 0 }, { 0, 0 },
}; };
static const struct cpu_driver model_15 __cpu_driver = { static const struct cpu_driver model_17 __cpu_driver = {
.ops = &cpu_dev_ops, .ops = &cpu_dev_ops,
.id_table = cpu_table, .id_table = cpu_table,
}; };

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@ -22,6 +22,7 @@
#define SOC_EARLY_VMTRR_TEMPRAM 2 #define SOC_EARLY_VMTRR_TEMPRAM 2
void picasso_init_cpus(struct device *dev); void picasso_init_cpus(struct device *dev);
int get_cpu_count(void);
void check_mca(void); void check_mca(void);
#endif /* __PICASSO_CPU_H__ */ #endif /* __PICASSO_CPU_H__ */

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@ -73,10 +73,6 @@
#define D18F1_VGAEN 0xf4 #define D18F1_VGAEN 0xf4
# define VGA_ADDR_ENABLE (1 << 0) # define VGA_ADDR_ENABLE (1 << 0)
/* D18F5 */
#define NB_CAPABILITIES2 0x84
#define CMP_CAP_MASK 0xff
void amd_initcpuio(void); void amd_initcpuio(void);
void domain_enable_resources(struct device *dev); void domain_enable_resources(struct device *dev);