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mainboard/[g-l]: add IS_ENABLED() around Kconfig symbol references 

Change-Id: I1f906c8c465108017bc4d08534653233078ef32d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Martin Roth 2017-06-24 21:53:37 -06:00
parent f95911ad37
commit 356b519049
52 changed files with 88 additions and 87 deletions
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4
src/mainboard/gigabyte/ga_2761gxdk/romstage.c
View File

@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

4
src/mainboard/gigabyte/m57sli/romstage.c
View File

@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -168,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

4
src/mainboard/gigabyte/ma785gm/romstage.c
View File

@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

4
src/mainboard/gigabyte/ma785gmt/romstage.c
View File

@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

4
src/mainboard/gigabyte/ma78gm/romstage.c
View File

@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/google/auron/smihandler.c
View File

@ -33,7 +33,7 @@ static u8 mainboard_smi_ec(void)
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);

2
src/mainboard/google/beltino/acpi_tables.c
View File

@ -72,7 +72,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->tpmp = 1;
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
// SuperIO is always RO
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif

2
src/mainboard/google/butterfly/romstage.c
View File

@ -34,7 +34,7 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <halt.h>
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
#include <vendorcode/google/chromeos/chromeos.h>
#endif
#include <cbfs.h>

2
src/mainboard/google/foster/chromeos.c
View File

@ -68,7 +68,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_recovery_mode_switch(void)
{
#if CONFIG_EC_GOOGLE_CHROMEEC
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
uint32_t ec_events;
ec_events = google_chromeec_get_events_b();

2
src/mainboard/google/link/acpi_tables.c
View File

@ -58,7 +58,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif

6
src/mainboard/google/link/mainboard.c
View File

@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
@ -52,7 +52,7 @@ void mainboard_post(u8 value)
*/
}
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 0;
@ -201,7 +201,7 @@ static void mainboard_enable(device_t dev)
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = link_onboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif

2
src/mainboard/google/link/mainboard_smi.c
View File

@ -33,7 +33,7 @@ static u8 mainboard_smi_ec(void)
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);

4
src/mainboard/google/nyan_blaze/romstage.c
View File

@ -53,7 +53,7 @@ static void __attribute__((noinline)) romstage(void)
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
#if !CONFIG_VBOOT
#if !IS_ENABLED(CONFIG_VBOOT)
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
@ -96,7 +96,7 @@ static void __attribute__((noinline)) romstage(void)
/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
void main(void)
{
#if !CONFIG_VBOOT
#if !IS_ENABLED(CONFIG_VBOOT)
asm volatile ("bl arm_init_caches"
::: "r0","r1","r2","r3","r4","r5","ip");
#endif

2
src/mainboard/google/parrot/acpi_tables.c
View File

@ -51,7 +51,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u1 = 0;
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif

8
src/mainboard/google/parrot/smihandler.c
View File

@ -29,7 +29,7 @@ static u8 mainboard_smi_ec(void)
{
u8 src;
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
static int battery_critical_logged;
#endif
@ -39,7 +39,7 @@ static u8 mainboard_smi_ec(void)
switch (src) {
case EC_BATTERY_CRITICAL:
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
if (!battery_critical_logged)
elog_add_event_byte(ELOG_TYPE_EC_EVENT,
EC_EVENT_BATTERY_CRITICAL);
@ -49,7 +49,7 @@ static u8 mainboard_smi_ec(void)
case EC_LID_CLOSE:
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */
@ -74,7 +74,7 @@ void mainboard_smi_gpi(u32 gpi_sts)
else if (gpi_sts & (1 << EC_LID_GPI)) {
printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, EC_EVENT_LID_CLOSED);
#endif
/* Go to S5 */

6
src/mainboard/google/rambi/mainboard.c
View File

@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
@ -40,7 +40,7 @@ void mainboard_suspend_resume(void)
{
}
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 1;
@ -169,7 +169,7 @@ static void mainboard_enable(device_t dev)
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif

2
src/mainboard/google/rambi/mainboard_smi.c
View File

@ -34,7 +34,7 @@ static uint8_t mainboard_smi_ec(void)
uint16_t pmbase = get_pmbase();
uint32_t pm1_cnt;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);

2
src/mainboard/google/slippy/acpi_tables.c
View File

@ -55,7 +55,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->tpmp = 1;
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif

2
src/mainboard/google/slippy/smihandler.c
View File

@ -41,7 +41,7 @@ static u8 mainboard_smi_ec(void)
u8 cmd = google_chromeec_get_event();
u32 pm1_cnt;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
/* Log this event */
if (cmd)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);

2
src/mainboard/google/storm/mainboard.c
View File

@ -31,7 +31,7 @@
static void setup_usb(void)
{
#if !CONFIG_BOARD_VARIANT_AP148
#if !IS_ENABLED(CONFIG_BOARD_VARIANT_AP148)
gpio_tlmm_config_set(USB_ENABLE_GPIO, FUNC_SEL_GPIO,
GPIO_PULL_UP, GPIO_10MA, GPIO_ENABLE);
gpio_set(USB_ENABLE_GPIO, 1);

2
src/mainboard/google/stout/acpi_tables.c
View File

@ -53,7 +53,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u1 = 0;
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
#endif

8
src/mainboard/google/stout/ec.c
View File

@ -76,7 +76,7 @@ void stout_ec_finalize_smm(void)
if (ec_reg & 0x8) {
printk(BIOS_ERR, " EC Fan Error\n");
critical_shutdown = 1;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_FAN_ERROR);
#endif
}
@ -86,7 +86,7 @@ void stout_ec_finalize_smm(void)
if (ec_reg & 0x80) {
printk(BIOS_ERR, " EC Thermal Device Error\n");
critical_shutdown = 1;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event_word(EC_EVENT_BATTERY_CRITICAL, EC_EVENT_THERMAL);
#endif
}
@ -98,14 +98,14 @@ void stout_ec_finalize_smm(void)
if ((ec_reg & 0xCF) == 0xC0) {
printk(BIOS_ERR, " EC Critical Battery Error\n");
critical_shutdown = 1;
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY_CRITICAL);
#endif
}
if ((ec_reg & 0x8F) == 0x8F) {
printk(BIOS_ERR, " EC Read Battery Error\n");
#if CONFIG_ELOG_GSMI
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event_word(ELOG_TYPE_EC_EVENT, EC_EVENT_BATTERY);
#endif
}

8
src/mainboard/hp/dl145_g1/romstage.c
View File

@ -88,7 +88,7 @@ int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/model_fxx/init_cpus.c"
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
#include "cpu/amd/model_fxx/fidvid.c"
#endif
@ -128,14 +128,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
ht_setup_chains_x(sysinfo);
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
struct cpuid_result cpuid1 = cpuid(0x80000007);
@ -191,7 +191,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
memreset_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
init_timer(); // Need to use TMICT to synchronize FID/VID
#endif
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);

2
src/mainboard/hp/dl145_g3/mptable.c
View File

@ -29,7 +29,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>

4
src/mainboard/hp/dl145_g3/romstage.c
View File

@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -166,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

2
src/mainboard/hp/dl165_g6_fam10/mptable.c
View File

@ -29,7 +29,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>

4
src/mainboard/hp/dl165_g6_fam10/romstage.c
View File

@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_other_cores_started(bsp_apicid);
#endif
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
View File

@ -169,7 +169,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

4
src/mainboard/iei/kino-780am2-fam10/romstage.c
View File

@ -139,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/intel/baskingridge/acpi_tables.c
View File

@ -74,7 +74,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->tpmp = 1;
#if CONFIG_CHROMEOS
#if IS_ENABLED(CONFIG_CHROMEOS)
/* Emerald Lake has no EC (?) */
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif

2
src/mainboard/intel/bayleybay_fsp/mainboard.c
View File

@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>

2
src/mainboard/intel/camelbackmountain_fsp/mainboard.c
View File

@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>

4
src/mainboard/intel/cougar_canyon2/romstage.c
View File

@ -213,7 +213,7 @@ void main(FSP_INFO_HEADER *fsp_info_header)
pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
post_code(0x46);
if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but
@ -261,7 +261,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
post_code(0x49);
#if CONFIG_USBDEBUG
#if IS_ENABLED(CONFIG_USBDEBUG)
/* FSP reconfigures USB, so reinit it to have debug */
early_usbdebug_init();
#endif

2
src/mainboard/intel/eagleheights/fadt.c
View File

@ -62,7 +62,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->dsdt = (unsigned long) dsdt;
fadt->preferred_pm_profile = 7; /* Performance Server */
fadt->sci_int = 0x9;
#if CONFIG_HAVE_SMI_HANDLER
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
fadt->smi_cmd = APM_CNT;
#else
fadt->smi_cmd = 0x00;

2
src/mainboard/iwill/dk8_htx/mptable.c
View File

@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>

4
src/mainboard/iwill/dk8_htx/romstage.c
View File

@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@ -112,7 +112,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);

4
src/mainboard/jetway/pa78vm5/romstage.c
View File

@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_early_setup();
sb7xx_51xx_early_setup();
#if CONFIG_SET_FIDVID
#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

2
src/mainboard/kontron/kt690/romstage.c
View File

@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();

7
src/mainboard/kontron/ktqm77/mainboard.c
View File

@ -21,7 +21,7 @@
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#include <x86emu/x86emu.h>
#endif
#include <pc80/mc146818rtc.h>
@ -31,7 +31,7 @@
#include <boot/coreboot_tables.h>
#include <southbridge/intel/bd82x6x/pch.h>
#if CONFIG_VGA_ROM_RUN
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
static int int15_handler(void)
{
int res = 0;
@ -164,7 +164,8 @@ static int int15_handler(void)
static void mainboard_enable(device_t dev)
{
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) || \
IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
#endif

2
src/mainboard/lenovo/g505s/buildOpts.c
View File

@ -169,7 +169,7 @@
#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
#if CONFIG_GFXUMA
#if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/

2
src/mainboard/lenovo/t400/romstage.c
View File

@ -94,7 +94,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* Check for S3 resume. */
const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
if (((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
s3resume = 1;
/* Clear SLP_TYPE. This will break stage2 but

2
src/mainboard/lenovo/x200/romstage.c
View File

@ -89,7 +89,7 @@ void mainboard_romstage_entry(unsigned long bist)
/* Check for S3 resume. */
const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
if (((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
s3resume = 1;
/* Clear SLP_TYPE. This will break stage2 but

2
src/mainboard/lenovo/x201/romstage.c
View File

@ -286,7 +286,7 @@ void mainboard_romstage_entry(unsigned long bist)
else
quick_ram_check();
#if CONFIG_LPC_TPM
#if IS_ENABLED(CONFIG_LPC_TPM)
init_tpm(s3resume);
#endif
}

2
src/mainboard/lippert/frontrunner/romstage.c
View File

@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
"returns 0xff\n", address);

4
src/mainboard/lippert/hurricane-lx/mainboard.c
View File

@ -25,7 +25,7 @@
#include <device/pci_ids.h>
/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
#if CONFIG_ONBOARD_UARTS_RS485
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x06
#else
#define SIO_GP1X_CONFIG 0x00
@ -54,7 +54,7 @@ static void init(struct device *dev)
outl(0x00000040, gpio_base + 0x04); // GPIO6 output 1 - LAN_PD#
outl(0x00000400, gpio_base + 0x34); // GPIO10 in aux1 1 - THRM_ALRM#
outl(0x00000400, gpio_base + 0x20); // GPIO10 input 1 - THRM_ALRM#
#if !CONFIG_BOARD_OLD_REVISION
#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
outl(0x00000800, gpio_base + 0x94); // GPIO27 out aux2 1 - 32kHz
outl(0x00000800, gpio_base + 0x84); // GPIO27 output 1 - 32kHz
#endif

8
src/mainboard/lippert/hurricane-lx/romstage.c
View File

@ -48,7 +48,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
return smbus_read_byte(device, address);
}
#if !CONFIG_BOARD_OLD_REVISION
#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
/* Send config data to System Management Controller via SMB. */
static int smc_send_config(unsigned char config_data)
{
@ -79,7 +79,7 @@ static const u16 sio_init_table[] = { // hi = data, lo = index
0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
#if !CONFIG_USE_WATCHDOG_ON_BOOT
#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
#endif
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins
@ -88,7 +88,7 @@ static const u16 sio_init_table[] = { // hi = data, lo = index
0x07C0, // enable Simple-I/O for GP12-10= RS485_EN2,1, WD_ACTIVE
0x06C8, // config GP12,11 as output, GP10 as input
0x2DF5, // map Hw Monitor Thermal Output to GP55
#if CONFIG_BOARD_OLD_REVISION
#if IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
0x1F2A, 0xC072, // switch GP13 to GPIO, WDT output from PWROK to KRST
#endif
};
@ -132,7 +132,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist)
cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
#if !CONFIG_BOARD_OLD_REVISION
#if !IS_ENABLED(CONFIG_BOARD_OLD_REVISION)
int err;
/* bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {

2
src/mainboard/lippert/literunner-lx/mainboard.c
View File

@ -25,7 +25,7 @@
#include <device/pci_ids.h>
/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
#if CONFIG_ONBOARD_UARTS_RS485
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x07
#else
#define SIO_GP1X_CONFIG 0x01

6
src/mainboard/lippert/literunner-lx/romstage.c
View File

@ -38,7 +38,7 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */
#if CONFIG_ONBOARD_IDE_SLAVE
#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE)
#define SMC_CONFIG 0x03
#else
#define SMC_CONFIG 0x01
@ -79,7 +79,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF)
printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
"returns 0xff\n", address);
@ -118,7 +118,7 @@ static const u16 sio_init_table[] = { // hi = data, lo = index
0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
#if !CONFIG_USE_WATCHDOG_ON_BOOT
#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
#endif
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins

2
src/mainboard/lippert/roadrunner-lx/mainboard.c
View File

@ -25,7 +25,7 @@
#include <device/pci_ids.h>
/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */
#if CONFIG_ONBOARD_UARTS_RS485
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x26
#else
#define SIO_GP1X_CONFIG 0x20

2
src/mainboard/lippert/roadrunner-lx/romstage.c
View File

@ -55,7 +55,7 @@ static const u16 sio_init_table[] = { // hi = data, lo = index
0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal
0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset
0x9072, // watchdog triggers PWROK, counts seconds
#if !CONFIG_USE_WATCHDOG_ON_BOOT
#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
#endif
0xBF25, 0x372A, 0xF326, // select GPIO function for most pins

2
src/mainboard/lippert/spacerunner-lx/mainboard.c
View File

@ -25,7 +25,7 @@
#include <device/pci_ids.h>
/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
#if CONFIG_ONBOARD_UARTS_RS485
#if IS_ENABLED(CONFIG_ONBOARD_UARTS_RS485)
#define SIO_GP1X_CONFIG 0x07
#else
#define SIO_GP1X_CONFIG 0x01

6
src/mainboard/lippert/spacerunner-lx/romstage.c
View File

@ -38,7 +38,7 @@
#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
/* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */
#if CONFIG_ONBOARD_IDE_SLAVE
#if IS_ENABLED(CONFIG_ONBOARD_IDE_SLAVE)
#define SMC_CONFIG 0x03
#else
#define SMC_CONFIG 0x01
@ -79,7 +79,7 @@ int spd_read_byte(unsigned int device, unsigned int address)
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
#if CONFIG_DEBUG_SMBUS
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
"returns 0xff\n", address);
@ -119,7 +119,7 @@ static const u16 sio_init_table[] = { // hi = data, lo = index
0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal
0x1423, // don't delay PoWeROK1/2
0x9072, // watchdog triggers PWROK, counts seconds
#if !CONFIG_USE_WATCHDOG_ON_BOOT
#if !IS_ENABLED(CONFIG_USE_WATCHDOG_ON_BOOT)
0x0073, 0x0074, // disarm watchdog by changing 56 s timeout to 0
#endif
0xBF25, 0x172A, 0xF326, // select GPIO function for most pins