mb/intel/adlrvp_m: add ec device entry to devicetree
TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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device domain 0 on
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device domain 0 on
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device pci 1f.0 on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end # eSPI
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device pci 1f.2 hidden
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device pci 1f.2 hidden
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# The pmc_mux chip driver is a placeholder for the
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# The pmc_mux chip driver is a placeholder for the
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