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soc/amd/cezanne: Enable uCode update 

TEST=Boot majolica and see microcode update
CBFS: Found 'cpu_microcode_blob.bin' @0x6900 size 0x15c0 in mcache @0xcf7fe9d8
microcode: patch id to apply = 0x0a50000b
microcode: being updated to patch id = 0x0a50000b succeeded

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If50b1d8b3ebf4b3e6f8a9dd3ab96073e0cb92424
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel 2021-02-12 16:04:27 -07:00 committed by Felix Held
parent 394c6b0922
commit 35dc4b0ede
2 changed files with 7 additions and 1 deletions
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5
src/soc/amd/cezanne/Kconfig
View File

@ -40,11 +40,14 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SPI select SOC_AMD_COMMON_BLOCK_SPI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_UCODE
select SSE2 select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select UDK_2017_BINDING select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
default 5568
config CHIPSET_DEVICETREE config CHIPSET_DEVICETREE
string string
default "soc/amd/cezanne/chipset.cb" default "soc/amd/cezanne/chipset.cb"

3
src/soc/amd/cezanne/cpu.c
View File

@ -2,6 +2,7 @@
#include <amdblocks/cpu.h> #include <amdblocks/cpu.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <device/device.h> #include <device/device.h>
@ -15,6 +16,8 @@ static void zen_2_3_init(struct device *dev)
{ {
setup_lapic(); setup_lapic();
set_cstate_io_addr(); set_cstate_io_addr();
amd_update_microcode_from_cbfs();
} }
static struct device_operations cpu_dev_ops = { static struct device_operations cpu_dev_ops = {