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mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 

Enable CNVi in devicetree and add gpio pad configs for CNVi

BUG=none
BRANCH=none
TEST=Build and boot tglrvp

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I71146960e0d53dae87946a0365dac6f224a72391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Srinidhi N Kaushik 2020-03-12 01:08:14 -07:00 committed by Patrick Georgi
parent 1f4f0b47f5
commit 3663d55a23
2 changed files with 5 additions and 1 deletions
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2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -130,7 +130,7 @@ chip soc/intel/tigerlake
device pci 0e.0 on end # VMD 0x9A0B device pci 0e.0 on end # VMD 0x9A0B
# From PCH EDS(576591) # From PCH EDS(576591)
device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
device pci 10.6 off end # THC0 0xA0D0 device pci 10.6 off end # THC0 0xA0D0
device pci 10.7 off end # THC1 0xA0D1 device pci 10.7 off end # THC1 0xA0D1
device pci 12.0 off end # SensorHUB 0xA0FC device pci 12.0 off end # SensorHUB 0xA0FC

4
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
View File

@ -61,6 +61,10 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPO(GPP_C5, 1, DEEP),
PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
/* CNVi */
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */
}; };
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */