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@ -55,9 +55,9 @@ void dimms_read(unsigned long x)
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eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_read: ");
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print_err_hex32(eax);
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print_err("\r\n");
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print_debug("dimms_read: ");
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print_debug_hex32(eax);
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print_debug("\r\n");
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y = * (volatile unsigned long *) eax;
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eax += 0x10000000;
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}
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@ -68,9 +68,9 @@ void dimms_write(int x)
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uint8_t c;
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unsigned long eax = x;
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for(c = 0; c < 6; c++) {
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print_err("dimms_write: ");
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print_err_hex32(eax);
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print_err("\r\n");
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print_debug("dimms_write: ");
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print_debug_hex32(eax);
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print_debug("\r\n");
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*(volatile unsigned long *) eax = 0;
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eax += 0x10000000;
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}
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@ -81,11 +81,11 @@ void dimms_write(int x)
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#ifdef DEBUG_SETNORTHB
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void setnorthb(device_t north, uint8_t reg, uint8_t val)
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{
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print_err("setnorth: reg ");
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print_err_hex8(reg);
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print_err(" to ");
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print_err_hex8(val);
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print_err("\r\n");
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print_debug("setnorth: reg ");
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print_debug_hex8(reg);
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print_debug(" to ");
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print_debug_hex8(val);
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print_debug("\r\n");
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pci_write_config8(north, reg, val);
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}
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#else
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@ -97,13 +97,13 @@ dumpnorth(device_t north)
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{
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uint8_t r, c;
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for(r = 0; r < 256; r += 16) {
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print_err_hex8(r);
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print_err(":");
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print_debug_hex8(r);
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print_debug(":");
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for(c = 0; c < 16; c++) {
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print_err_hex8(pci_read_config8(north, r+c));
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print_err(" ");
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print_debug_hex8(pci_read_config8(north, r+c));
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print_debug(" ");
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}
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print_err("\r\n");
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print_debug("\r\n");
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}
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}
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@ -120,22 +120,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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device_t north = (device_t) 0;
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uint8_t c, r;
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print_err("vt8601 init starting\n");
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print_err("vt8601 init starting\r\n");
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north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
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north = 0;
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print_err_hex32(north);
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print_err(" is the north\n");
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print_err_hex16(pci_read_config16(north, 0));
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print_err(" ");
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print_err_hex16(pci_read_config16(north, 2));
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print_err("\r\n");
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print_debug_hex32(north);
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print_debug(" is the north\n");
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print_debug_hex16(pci_read_config16(north, 0));
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print_debug(" ");
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print_debug_hex16(pci_read_config16(north, 2));
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print_debug("\r\n");
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/* All we are doing now is setting initial known-good values that will
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* be revised later as we read SPD
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*/
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// memory clk enable. We are not using ECC
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pci_write_config8(north,0x78, 0x01);
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print_err_hex8(pci_read_config8(north, 0x78));
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print_debug_hex8(pci_read_config8(north, 0x78));
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// dram control, see the book.
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#if DIMM_PC133
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pci_write_config8(north,0x68, 0x52);
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@ -146,7 +146,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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pci_write_config8(north,0x6B, 0x0c);
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// Initial setting, 256MB in each bank, will be rewritten later.
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pci_write_config8(north,0x5A, 0x20);
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print_err_hex8(pci_read_config8(north, 0x5a));
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print_debug_hex8(pci_read_config8(north, 0x5a));
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pci_write_config8(north,0x5B, 0x40);
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pci_write_config8(north,0x5C, 0x60);
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pci_write_config8(north,0x5D, 0x80);
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@ -220,11 +220,15 @@ do_module_size(unsigned char slot /*, unsigned char base) */)
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/* is the module there? if byte 2 is not 4, then we'll assume it
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* is useless.
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*/
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if (smbus_read_byte(module, 2) != 4)
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if (smbus_read_byte(module, 2) != 4) {
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print_err("Slot ");
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print_err_hex8(slot);
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print_err(" is empty\r\n");
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goto done;
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}
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//print_err_hex8(slot);
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// print_err(" is SDRAM\n");
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//print_debug_hex8(slot);
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// print_debug(" is SDRAM\n");
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width = smbus_read_byte(module, 6) | (smbus_read_byte(module,7)<<0);
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banks = smbus_read_byte(module, 17);
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/* we're going to assume symmetric banks. Sorry. */
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@ -239,15 +243,15 @@ do_module_size(unsigned char slot /*, unsigned char base) */)
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value -= 23;
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/* now subtract 3 more bits as these are 8-bit bytes */
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value -= 3;
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// print_err_hex8(value);
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// print_err(" is the # bits for this bank\n");
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// print_debug_hex8(value);
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// print_debug(" is the # bits for this bank\n");
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/* now put that size into the correct register */
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value = (1 << value);
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done:
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reg = ramregs[slot];
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// print_err_hex8(value); print_err(" would go into ");
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// print_err_hex8(ramregs[reg]); print_err("\n");
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// print_debug_hex8(value); print_debug(" would go into ");
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// print_debug_hex8(ramregs[reg]); print_debug("\n");
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// pci_write_config8(north, ramregs[reg], value);
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return value;
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}
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@ -272,7 +276,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
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print_err_hex8(val); print_err(" is the computed timing\n");
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print_debug_hex8(val); print_debug(" is the computed timing\n");
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/* don't set it. Experience shows that this screwy chipset should just
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* be run with the most conservative timing.
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* pci_write_config8(0, 0x64, val);
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@ -299,19 +303,19 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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/* set NOP*/
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pci_write_config8(north,0x6C, 0x01);
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print_err("NOP\r\n");
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print_debug("NOP\r\n");
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/* wait 200us*/
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// You need to do the memory reference. That causes the nop cycle.
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dimms_read(0);
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udelay(400);
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print_err("PRECHARGE\r\n");
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print_debug("PRECHARGE\r\n");
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/* set precharge */
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pci_write_config8(north,0x6C, 0x02);
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print_err("DUMMY READS\r\n");
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print_debug("DUMMY READS\r\n");
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/* dummy reads*/
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dimms_read(0);
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udelay(200);
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print_err("CBR\r\n");
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print_debug("CBR\r\n");
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/* set CBR*/
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pci_write_config8(north,0x6C, 0x04);
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@ -332,7 +336,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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udelay(200);
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dimms_read(0);
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udelay(200);
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print_err("MRS\r\n");
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print_debug("MRS\r\n");
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/* set MRS*/
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pci_write_config8(north,0x6c, 0x03);
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#if DIMM_CL2
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@ -341,21 +345,21 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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dimms_read(0x1d0);
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#endif
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udelay(200);
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print_err("NORMAL\r\n");
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print_debug("NORMAL\r\n");
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/* set to normal mode */
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pci_write_config8(north,0x6C, 0x08);
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dimms_write(0x55aa55aa);
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dimms_read(0);
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udelay(200);
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print_err("set ref. rate\r\n");
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print_debug("set ref. rate\r\n");
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// Set the refresh rate.
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#if DIMM_PC133
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pci_write_config8(north,0x6A, 0x86);
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#else
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pci_write_config8(north,0x6A, 0x65);
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#endif
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print_err("enable multi-page open\r\n");
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print_debug("enable multi-page open\r\n");
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// enable multi-page open
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pci_write_config8(north,0x6B, 0x0d);
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@ -374,21 +378,21 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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pci_write_config8(north,0x56, 0xff);
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pci_write_config8(north,0x57, 0xff);
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dumpnorth(north);
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print_err("MA\r\n");
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print_debug("MA\r\n");
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for(c = 0; c < 8; c++) {
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/* Write different values to 0 and 8, then read from 0.
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* If values of address 0 match, we have something there. */
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print_err("write to 0\r\n");
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print_debug("write to 0\r\n");
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*(volatile unsigned long *) 0 = 0x12345678;
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/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
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* WILL FOOL YOU!
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*/
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print_err("write to 8\r\n");
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print_debug("write to 8\r\n");
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*(volatile unsigned long *) 8 = 0x87654321;
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if (*(volatile unsigned long *) 0 != 0x12345678) {
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print_err("no memory in this bank\r\n");
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print_debug("no memory in this bank\r\n");
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/* No memory in this bank. Tell it to the bridge. */
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pci_write_config8(north,ramregs[c], 0);
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}
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@ -404,7 +408,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
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* (volatile unsigned long *) eax = 0;
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print_err(" done write to eax\r\n");
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print_debug(" done write to eax\r\n");
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// Write to addresses with only one address bit
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// on, from 0x80000000 to 0x00000008 (lower 3 bits
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// are ignored, assuming 64-bit bus). Then what
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@ -416,20 +420,20 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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eax = 0x80000000;
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while (eax != 4) {
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* (volatile unsigned long *) eax = eax;
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//print_err_hex32(eax);
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//print_debug_hex32(eax);
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outb(eax&0xff, 0x80);
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eax >>= 1;
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}
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print_err(" done read to eax\r\n");
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print_debug(" done read to eax\r\n");
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|
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eax = * (unsigned long *)0;
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|
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/* oh boy ... what is this.
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movl 0, %eax
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cmpl %eax, %esi
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jnc 3f
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*/
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print_err("eax and esi: ");
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print_err_hex32(eax); print_err(" ");
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print_err_hex32(esi); print_err("\r\n");
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|
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print_debug("eax and esi: ");
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|
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print_debug_hex32(eax); print_debug(" ");
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|
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print_debug_hex32(esi); print_debug("\r\n");
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|
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if (eax > esi) { /* ??*/
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@ -441,9 +445,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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}
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|
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pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
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print_err("enabled first bank of ram ... ma is ");
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print_err_hex8(pci_read_config8(north, 0x58));
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print_err("\r\n");
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|
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print_debug("enabled first bank of ram ... ma is ");
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print_debug_hex8(pci_read_config8(north, 0x58));
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|
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print_debug("\r\n");
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|
|
}
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|
|
}
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|
|
base = 0;
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|
|
@ -475,7 +479,9 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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|
|
base = do_module_size(0xa0, base);
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|
base = do_module_size(0xa0, base);
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|
|
base = do_module_size(0xa0, base);*/
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|
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|
|
print_err("vt8601 done\n");
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|
|
print_err("vt8601 done\r\n");
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|
|
/*
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|
|
dumpnorth(north);
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|
|
udelay(1000);
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|
|
*/
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|
}
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