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AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0 

Change-Id: I65fad1cfba95f0ee1ed3f7f7a57d874144da1e40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8561
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
This commit is contained in:
Kyösti Mälkki 2015-02-05 15:43:23 +02:00
parent 7748ee5ee1
commit 3690727955
4 changed files with 2 additions and 14 deletions
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3
src/northbridge/amd/amdfam10/Kconfig
View File

@ -64,9 +64,6 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
config SB_HT_CHAIN_ON_BUS0
def_bool y
config HT_CHAIN_DISTRIBUTE
def_bool n

5
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -216,7 +216,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
* so we set the subordinate bus number to 0xff for the moment.
*/
if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink)
if (!is_sblink)
max++;
/* One node can have 8 link and segn is the same. */
@ -280,9 +280,6 @@ static void relocate_sb_ht_chain(void)
struct bus *link, *prev = NULL;
u8 sblink;
if (!CONFIG_SB_HT_CHAIN_ON_BUS0)
return;
dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
sblink = (pci_read_config32(dev, 0x64)>>8) & 7;
link = dev->link_list;

3
src/northbridge/amd/amdk8/Kconfig
View File

@ -64,9 +64,6 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY
bool
default n
config SB_HT_CHAIN_ON_BUS0
def_bool y
config HT_CHAIN_DISTRIBUTE
def_bool n

5
src/northbridge/amd/amdk8/northbridge.c
View File

@ -179,7 +179,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
* so we set the subordinate bus number to 0xff for the moment.
*/
if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink)
if (!is_sblink)
max++;
/* Second chain will be on 0x40, third 0x80, forth 0xc0. */
@ -249,9 +249,6 @@ static void relocate_sb_ht_chain(void)
struct bus *link, *prev = NULL;
u8 sblink;
if (!CONFIG_SB_HT_CHAIN_ON_BUS0)
return;
dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
link = dev->link_list;