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soc/intel/alderlake: Disable hwp scalibility tracking 

Disable scalability tracking for autonomous frequency control in
order to improve power and performance.

BUG=b:280021171
TEST=Boot to OS on brya0

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If71ee5374c67611b32691bbec4effdf828b3e566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74723
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Bora Guvendik 2023-04-24 18:22:55 -07:00 committed by Nick Vaccaro
parent 6e64c01d08
commit 3708f54bb5
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/alderlake/chipset.cb
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@ -96,6 +96,9 @@ chip soc/intel/alderlake
# Disable SaGV reordering operation to start with SaGV point 4 and reduce boot time.
register "disable_sagv_reorder" = "true"
# Disable hwp scalability tracking.
register "enable_hwp_scalability_tracking" = "false"
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.