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soc/intel/cmn/gfx: Join MBUS while FSP-S performs GFX init 

This patch calls into the function to join the MBUS if the GFX PEIM
module inside the FSP binary is taking care of graphics initialization
based on the RUN_FSP_GOP config option. The FW skips joining the MBUS
in case of a non-FSP solution and/or SOC_INTEL_GFX_MBUS_JOIN config is
not enabled.

BUG=b:284799726
TEST=MBUS joining is only applicable for google/rex while using GFX
PEIM.

Change-Id: I50d719a286722f5aafbad48ab4ca60500c836dd6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Subrata Banik 2023-11-02 00:31:45 +05:30
parent ebd4c3d113
commit 370b2335df
1 changed files with 32 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
src/soc/intel/common/block/graphics/graphics.c
View File

@ -280,31 +280,42 @@ static void graphics_dev_read_resources(struct device *dev)
} }
} }
static void graphics_join_mbus(void)
{
enum display_type type = get_external_display_status();
uint32_t hashing_mode = 0; /* 2x2 */
if (type == INTERNAL_DISPLAY_ONLY) {
hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */
/* Only eDP pipes is joining the MBUS */
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
} else if (type == DUAL_DISPLAY) {
/* All pipes are joining the MBUS */
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_B), PIPE_B, GFX_MBUS_JOIN | hashing_mode);
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_C), PIPE_C, GFX_MBUS_JOIN | hashing_mode);
#if CONFIG(INTEL_GMA_VERSION_2)
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_D), PIPE_D, GFX_MBUS_JOIN | hashing_mode);
#endif
} else {
/* No pipe joins the MBUS */
graphics_gtt_rmw(GFX_MBUS_CTL, GFX_MBUS_JOIN_PIPE_SEL,
GFX_MBUS_JOIN | hashing_mode);
}
}
static void graphics_dev_final(struct device *dev) static void graphics_dev_final(struct device *dev)
{ {
pci_dev_request_bus_master(dev); pci_dev_request_bus_master(dev);
if (CONFIG(SOC_INTEL_GFX_MBUS_JOIN)) { /*
enum display_type type = get_external_display_status(); * Call function to join the MBUS if GFX PEIM module inside FSP
uint32_t hashing_mode = 0; /* 2x2 */ * binary is taking care of graphics initialization based on
if (type == INTERNAL_DISPLAY_ONLY) { * RUN_FSP_GOP config option.
hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */ *
/* Only eDP pipes is joining the MBUS */ * Skip FW joining the MBUS in case of non-FSP solution.
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode); */
} else if (type == DUAL_DISPLAY) { if (CONFIG(RUN_FSP_GOP) && CONFIG(SOC_INTEL_GFX_MBUS_JOIN) && display_init_required())
/* All pipes are joining the MBUS */ graphics_join_mbus();
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_B), PIPE_B, GFX_MBUS_JOIN | hashing_mode);
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_C), PIPE_C, GFX_MBUS_JOIN | hashing_mode);
#if CONFIG(INTEL_GMA_VERSION_2)
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_D), PIPE_D, GFX_MBUS_JOIN | hashing_mode);
#endif
} else {
/* No pipe joins the MBUS */
graphics_gtt_rmw(GFX_MBUS_CTL, GFX_MBUS_JOIN_PIPE_SEL,
GFX_MBUS_JOIN | hashing_mode);
}
}
} }
const struct device_operations graphics_ops = { const struct device_operations graphics_ops = {