soc/intel/.../Kconfig: Move GPIO debug option into debug menu
Rename DEBUG_SOC_COMMON_BLOCK_GPIO to DEBUG_GPIO and move it into the Debugging menu. Change-Id: I737d0ee7fb5423b6d16d611a144d43fd3f168a2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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@ -693,6 +693,13 @@ config FATAL_ASSERTS
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help
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If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
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config HAVE_DEBUG_GPIO
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bool
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config DEBUG_GPIO
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bool "Output verbose GPIO debug messages"
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depends on HAVE_DEBUG_GPIO
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config DEBUG_CBFS
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bool "Output verbose CBFS debug messages"
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default n
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@ -1,15 +1,9 @@
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config SOC_INTEL_COMMON_BLOCK_GPIO
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bool
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select HAVE_DEBUG_GPIO
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help
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Intel Processor common GPIO support
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config DEBUG_SOC_COMMON_BLOCK_GPIO
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depends on SOC_INTEL_COMMON_BLOCK_GPIO
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bool "Output verbose GPIO debug messages"
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default n
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help
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This option enables GPIO debug messages
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# Use to program Interrupt Polarity Control (IPCx) register
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# Each bit represents IRQx Active High Polarity Disable configuration:
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# when set to 1, the interrupt polarity associated with IRQx is inverted
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@ -265,7 +265,7 @@ static void gpio_configure_pad(const struct pad_config *cfg)
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soc_pad_conf &= mask[i];
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soc_pad_conf |= pad_conf & ~mask[i];
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if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO))
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if (IS_ENABLED(CONFIG_DEBUG_GPIO))
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printk(BIOS_DEBUG,
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"gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
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" : 0x%08x]\n",
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@ -533,7 +533,7 @@ void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d)
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MISCCFG_GPE0_DW1_MASK |
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MISCCFG_GPE0_DW0_MASK);
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if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO))
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if (IS_ENABLED(CONFIG_DEBUG_GPIO))
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printk(BIOS_DEBUG, "misccfg_mask:%x misccfg_value:%x\n",
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misccfg_mask, misccfg_value);
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comm = soc_gpio_get_community(&gpio_communities);
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@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS
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select BOOTBLOCK_CONSOLE
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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select DEBUG_GPIO
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select POSTCAR_CONSOLE
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_RESET
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@ -50,7 +51,6 @@ config CPU_SPECIFIC_OPTIONS
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# select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select DEBUG_SOC_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_PCR
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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