soc/mediatek/mt8183: Fix pq module size config

For pq module size registers such as DISP_AAL_SIZE, the high bits
should be HSIZE, while low bits should be VSIZE. Fix the incorrect
settings for these registers where width and height are reversed.

According to MediaTek, there is no practical impact on mt8183 devices,
but it's still nice to get this fixed to avoid future confusion.

BUG=b:171167210
TEST=none
BRANCH=kukui

Change-Id: I4b6aedf9a3ca133fcbe9cb88b99a13d228233e24
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46626
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu 2020-10-21 18:23:03 +08:00 committed by Patrick Georgi
parent 279c3e1e7d
commit 37765930ec
1 changed files with 1 additions and 1 deletions

View File

@ -34,7 +34,7 @@ static void ovl_bgclr_in_sel(u32 idx)
static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height, static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height,
int enable_relay) int enable_relay)
{ {
write32(&regs->size, height << 16 | width); write32(&regs->size, width << 16 | height);
if (enable_relay) if (enable_relay)
write32(&regs->cfg, PQ_RELAY_MODE); write32(&regs->cfg, PQ_RELAY_MODE);
write32(&regs->en, PQ_EN); write32(&regs->en, PQ_EN);