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AMD Hudson/Yangtze: Enable support for SATA port multipliers 

This patch sets a bit in the Yangtze southbridge to enable
the extra protocol necessary to handle port multiplier chips.
This has been turned on during most of Kabini development
without any notable impact. Olive Hill has an optional daughter
board that incorporates Silicon Image Steel Vines chips.  This
change has been tested with and without the daughter board.  This
change can be regression tested using any Hudson-based motherboard,
although it has no impact on boards with discreet Hudson/Bolton
southbridges.

This was tested for impact on SATA performance in the absence of
a port multiplier using the IOZone benchmarks within the Phoronix
Test Suite.  A SATA 3 hard drive (6.0 Gbps) and an SSD were
connected to the ports on Olive Hill without using the port
multiplier card.  The test results contained more run-to-run
variation within the same configuration than was seen in the
aggregate results comparing the interface with and without the
port multiplier protocol additions.  In other words, the test
had less accuracy than the impact caused by turning on port
multiplier support.

Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3808
Tested-by: build bot (Jenkins)
This commit is contained in:
Bruce Griffith 2013-07-23 11:50:12 -06:00 committed by Stefan Reinauer
parent 915714501b
commit 37a1d6c955
1 changed files with 29 additions and 1 deletions
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30
src/southbridge/amd/agesa/hudson/sata.c
View File

@ -29,7 +29,35 @@
static void sata_init(struct device *dev) static void sata_init(struct device *dev)
{ {
} #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
/**************************************
* Configure the SATA port multiplier *
**************************************/
#define BYTE_TO_DWORD_OFFSET(x) (x/4)
#define AHCI_BASE_ADDRESS_REG 0x24
#define MISC_CONTROL_REG 0x40
#define UNLOCK_BIT (1<<0)
#define SATA_CAPABILITIES_REG 0xFC
#define CFG_CAP_SPM (1<<12)
volatile u32 *ahci_ptr =
(u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
u32 temp;
/* unlock the write-protect */
temp = pci_read_config32(dev, MISC_CONTROL_REG);
temp |= UNLOCK_BIT;
pci_write_config32(dev, MISC_CONTROL_REG, temp);
/* set the SATA AHCI mode to allow port expanders */
*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
/* lock the write-protect */
temp = pci_read_config32(dev, MISC_CONTROL_REG);
temp &= ~UNLOCK_BIT;
pci_write_config32(dev, MISC_CONTROL_REG, temp);
#endif
};
static struct pci_operations lops_pci = { static struct pci_operations lops_pci = {
/* .set_subsystem = pci_dev_set_subsystem, */ /* .set_subsystem = pci_dev_set_subsystem, */