chromeec: Support accessing memmap data over port 62/66
Some platforms cannot access the 900h-9ffh region over the LPC bus, so it's necessary to access memmap data over the ACPI cmd / data ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d Original-Reviewed-on: https://chromium-review.googlesource.com/262314 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Shawn Nematbakhsh
Patrick Georgi
parent
235f92203b
commit
37b7a666a2
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@ -3,6 +3,14 @@ config EC_GOOGLE_CHROMEEC
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help
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Google's Chrome EC
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config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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depends on EC_GOOGLE_CHROMEEC_LPC
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def_bool n
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help
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When defined, ACPI accesses EC memmap data on ports 66h/62h. When
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not defined, the memmap data is instead accessed on 900h-9ffh via
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the LPC bus.
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config EC_GOOGLE_CHROMEEC_I2C
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depends on EC_GOOGLE_CHROMEEC
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bool
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@ -41,7 +41,7 @@ Device (EC0)
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Name (DWRN, 15) // Battery capacity warning at 15%
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Name (DLOW, 10) // Battery capacity low at 10%
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OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
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OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN)
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Field (ERAM, ByteAcc, Lock, Preserve)
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{
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Offset (0x00),
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@ -56,48 +56,16 @@ Device (EC0)
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CHGL, 8, // Charger Current Limit
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}
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#if CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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OperationRegion (EMEM, EmbeddedControl,
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EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE)
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Field (EMEM, ByteAcc, Lock, Preserve)
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#else
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OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
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Field (EMEM, ByteAcc, NoLock, Preserve)
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#endif
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{
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Offset (0x00),
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TIN0, 8, // Temperature 0
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TIN1, 8, // Temperature 1
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TIN2, 8, // Temperature 2
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TIN3, 8, // Temperature 3
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TIN4, 8, // Temperature 4
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TIN5, 8, // Temperature 5
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TIN6, 8, // Temperature 6
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TIN7, 8, // Temperature 7
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TIN8, 8, // Temperature 8
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TIN9, 8, // Temperature 9
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Offset (0x10),
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FAN0, 16, // Fan Speed 0
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Offset (0x30),
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LIDS, 1, // Lid Switch State
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PBTN, 1, // Power Button Pressed
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WPDI, 1, // Write Protect Disabled
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RECK, 1, // Keyboard Initiated Recovery
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RECD, 1, // Dedicated Recovery Mode
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Offset (0x40),
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BTVO, 32, // Battery Present Voltage
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BTPR, 32, // Battery Present Rate
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BTRA, 32, // Battery Remaining Capacity
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ACEX, 1, // AC Present
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BTEX, 1, // Battery Present
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BFDC, 1, // Battery Discharging
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BFCG, 1, // Battery Charging
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BFCR, 1, // Battery Level Critical
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Offset (0x50),
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BTDA, 32, // Battery Design Capacity
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BTDV, 32, // Battery Design Voltage
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BTDF, 32, // Battery Last Full Charge Capacity
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BTCC, 32, // Battery Cycle Count
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BMFG, 64, // Battery Manufacturer String
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BMOD, 64, // Battery Model String
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BSER, 64, // Battery Serial String
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BTYP, 64, // Battery Type String
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Offset (0x80),
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ALS0, 16, // ALS reading 0 in lux
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#include "emem.asl"
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}
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Method (TINS, 1, Serialized)
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@ -0,0 +1,62 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* EMEM data may be accessed through port 62/66 or through LPC at 900h.
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*/
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Offset (0x00),
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TIN0, 8, // Temperature 0
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TIN1, 8, // Temperature 1
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TIN2, 8, // Temperature 2
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TIN3, 8, // Temperature 3
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TIN4, 8, // Temperature 4
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TIN5, 8, // Temperature 5
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TIN6, 8, // Temperature 6
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TIN7, 8, // Temperature 7
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TIN8, 8, // Temperature 8
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TIN9, 8, // Temperature 9
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Offset (0x10),
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FAN0, 16, // Fan Speed 0
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Offset (0x30),
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LIDS, 1, // Lid Switch State
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PBTN, 1, // Power Button Pressed
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WPDI, 1, // Write Protect Disabled
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RECK, 1, // Keyboard Initiated Recovery
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RECD, 1, // Dedicated Recovery Mode
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Offset (0x40),
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BTVO, 32, // Battery Present Voltage
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BTPR, 32, // Battery Present Rate
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BTRA, 32, // Battery Remaining Capacity
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ACEX, 1, // AC Present
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BTEX, 1, // Battery Present
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BFDC, 1, // Battery Discharging
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BFCG, 1, // Battery Charging
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BFCR, 1, // Battery Level Critical
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Offset (0x50),
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BTDA, 32, // Battery Design Capacity
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BTDV, 32, // Battery Design Voltage
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BTDF, 32, // Battery Last Full Charge Capacity
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BTCC, 32, // Battery Cycle Count
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BMFG, 64, // Battery Manufacturer String
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BMOD, 64, // Battery Model String
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BSER, 64, // Battery Serial String
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BTYP, 64, // Battery Type String
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Offset (0x80),
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ALS0, 16, // ALS reading 0 in lux
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