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src/mainboard/pcengines/apu1: Enable LPC TPM 

PC Engines apu1 has a 20 pin LPC header that allows connection of
external TPM module.

Add necessary Kconfig option and devicetree entry for TPM.

Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30354
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Michał Żygowski 2018-12-21 11:46:09 +01:00 committed by Kyösti Mälkki
parent 760970fb38
commit 37d4ffb0a5
2 changed files with 4 additions and 0 deletions
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1
src/mainboard/pcengines/apu1/Kconfig
View File

@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_2048 select BOARD_ROMSIZE_KB_2048
select GENERIC_SPD_BIN select GENERIC_SPD_BIN
select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS
select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR config MAINBOARD_DIR
string string

3
src/mainboard/pcengines/apu1/devicetree.cb
View File

@ -70,6 +70,9 @@ chip northbridge/amd/agesa/family14/root_complex
device pnp 2e.607 off end device pnp 2e.607 off end
device pnp 2e.e off end device pnp 2e.e off end
end end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end # LPC TPM
end #LPC end #LPC
device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1
device pci 14.5 off end # OHCI FS/LS USB device pci 14.5 off end # OHCI FS/LS USB