Documentation: Add x86 bootblock support
Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13441 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Lee Leahy
Leroy P Leahy
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380e167680
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@ -17,6 +17,7 @@
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<li>SoC <a href="#RequiredFiles">Required Files</a></li>
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<li><a href="#Descriptor">Start Booting</a></li>
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<li><a href="#EarlyDebug">Early Debug</a></li>
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<li><a href="#Bootblock">Bootblock</a></li>
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</ol>
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@ -99,6 +100,101 @@ mv build/coreboot.rom.new build/coreboot.rom
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</ul>
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<hr>
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<h1><a name="Bootblock">Bootblock</a></h1>
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<p>
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Implement the bootblock using the following steps:
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</p>
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<ol>
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<li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li>
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<li>Add the timestamp.inc file which initializes the floating point registers and saves
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the initial timestamp.
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</li>
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<li>Add the bootblock.c file which:
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<ol type="A">
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<li>Enables memory-mapped PCI config access</li>
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<li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
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<li>Enable ROM caching</li>
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</ol>
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</li>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file
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<ol type="A">
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<li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
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<li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
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</ol>
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</li>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file
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<ol type="A">
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<li>Add the bootblock subdirectory</li>
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</ol>
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</li>
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<li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file
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<ol type="A">
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<li>Add the fsp/memmap.h include file</li>
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<li>Add the mmap_region_granularity routine</li>
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</ol>
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</li>
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<li>Add the necessary .h files to define the necessary values and structures</li>
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<li>When successful port 0x80 will output the following values:
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<ol type="A">
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<li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
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- Bootblock successfully executed the
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
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and entered the 16-bit code at
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
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</li>
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<li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
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- Bootblock executing in
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
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</li>
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<li>0x10 - Verstage/romstage reached 32-bit mode</li>
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</ol>
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</li>
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</ol>
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<p>
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<b>Build Note:</b> The following files are included into the default bootblock image:
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</p>
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<ul>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
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and includes the following files:
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<ul>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
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<li>The code in
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
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includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the
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CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
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<li>The code in
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
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invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
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<ul>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
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<li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
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src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c
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</li>
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</ul>
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</li>
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</ul>
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
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</li>
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<li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
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added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
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</li>
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</ul>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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@ -69,6 +69,7 @@
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</li>
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<li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
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<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
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<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
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</ol>
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