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mb/google/brya/var/marasov: Disable USB2 PHY SUS well power gating 

The patch disables PCH USB2 PHY power gating to prevent possible
display flicker issue. Please refer Intel doc#723158 for more information.

BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Verify the build for marasov board

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frank Chu 2023-04-21 14:33:24 +08:00 committed by Felix Held
parent 870eca2052
commit 3810705ef0
1 changed files with 5 additions and 0 deletions
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5
src/mainboard/google/brya/variants/marasov/overridetree.cb
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@ -85,6 +85,11 @@ chip soc/intel/alderlake
.v1p05_icc_max_ma = 500,
.vnn_sx_voltage_mv = 1250,
}"
# As per Intel Advisory doc#723158, the change is required to prevent possible
# display flickering issue.
register "usb2_phy_sus_pg_disable" = "1"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,