GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/stoneyridge: Remove duplicate LPC decode setup 

Delete the LPC I/O decode configuration from fixme.c.  This code is
superseded by early_setup.c.

Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson 2017-10-27 17:12:43 -06:00
parent 7d06a3fe5a
commit 383ef6eef8
1 changed files with 0 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/amd/stoneyridge/fixme.c
View File

@ -66,8 +66,6 @@ void amd_initcpuio(void)
void amd_initmmio(void) void amd_initmmio(void)
{ {
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* /*
@ -79,11 +77,6 @@ void amd_initmmio(void)
| 1; | 1;
LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader); LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xff03ffd5;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, PCU_DEV, LPC_FUNC, 0x44);
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Set ROM cache onto WP to decrease post time */ /* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader); LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader);