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soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE 

With enabling FSP Notify Phase APIs, it has chance to issue a global
reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY
), which CSE already in idle mode and cause failure. For this reason we
should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select
SOC_INTEL_CSE_SEND_EOP_LATE instead.

BUG=b:261544011
BRANCH=firmware-brya-14505.B
TEST=tested and verified on Marasov, make sure this kind of global
reset can be executed successfully.

Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tracy Wu 2022-12-22 16:28:15 +08:00 committed by Martin L Roth
parent 2a12b6a9a4
commit 387ec919d9
1 changed files with 1 additions and 2 deletions
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3
src/soc/intel/alderlake/Kconfig
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@ -117,8 +117,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CSE_SEND_EOP_EARLY if !SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_CSE_SEND_EOP_LATE if SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_CSE_SEND_EOP_LATE
select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select HAVE_INTEL_COMPLIANCE_TEST_MODE