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cpu/amd/family_10h-family_15h: Set LDT tristate correctly on C32 sockets 

The existing code unconditionally cleared the LDT tristate enable bit,
which was incorrect for C32 sockets.  Update the code to be in line
with the BKDG recommendations.

Change-Id: I8095931973ea10f1467a6621092e88c6c494565a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13142
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Timothy Pearson 2015-11-24 14:11:47 -06:00 committed by Martin Roth
parent 6aa6eab98b
commit 39495bae5f
2 changed files with 39 additions and 19 deletions
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19
src/cpu/amd/family_10h-family_15h/defaults.h
View File

@ -260,25 +260,6 @@ static const struct {
{ 0, 0xE4, AMD_FAM10_ALL, AMD_PTYPE_ALL,
0x00002000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
/* FIXME
* Non-C32 packages only
*/
{ 0, 0x84, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
{ 0, 0xA4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
{ 0, 0xC4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
{ 0, 0xE4, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x00002000 }, /* [13] LdtStopTriEn = 1 */
/* FIXME
* C32 package is not supported at this time
*/
/* Link Global Retry Control Register */
{ 0, 0x150, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
0x00073900, 0x00073f70 }, /* TotalRetryAttempts = 0x7,

39
src/cpu/amd/family_10h-family_15h/init_cpus.c
View File

@ -1095,6 +1095,45 @@ static void cpuSetAMDPCI(u8 node)
}
}
if (is_fam15h()) {
if (CONFIG_CPU_SOCKET_TYPE == 0x14) {
/* Socket C32 */
dword = pci_read_config32(NODE_PCI(node, 0), 0x84);
dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
pci_write_config32(NODE_PCI(node, 0), 0x84, dword);
dword = pci_read_config32(NODE_PCI(node, 0), 0xa4);
dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
pci_write_config32(NODE_PCI(node, 0), 0xa4, dword);
dword = pci_read_config32(NODE_PCI(node, 0), 0xc4);
dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
pci_write_config32(NODE_PCI(node, 0), 0xc4, dword);
dword = pci_read_config32(NODE_PCI(node, 0), 0xe4);
dword |= 0x1 << 13; /* LdtStopTriEn = 1 */
pci_write_config32(NODE_PCI(node, 0), 0xe4, dword);
}
else {
/* Other socket (G34, etc.) */
dword = pci_read_config32(NODE_PCI(node, 0), 0x84);
dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
pci_write_config32(NODE_PCI(node, 0), 0x84, dword);
dword = pci_read_config32(NODE_PCI(node, 0), 0xa4);
dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
pci_write_config32(NODE_PCI(node, 0), 0xa4, dword);
dword = pci_read_config32(NODE_PCI(node, 0), 0xc4);
dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
pci_write_config32(NODE_PCI(node, 0), 0xc4, dword);
dword = pci_read_config32(NODE_PCI(node, 0), 0xe4);
dword &= ~(0x1 << 13); /* LdtStopTriEn = 0 */
pci_write_config32(NODE_PCI(node, 0), 0xe4, dword);
}
}
#ifdef DEBUG_HT_SETUP
/* Dump link settings */
for (i = 0; i < 4; i++) {