northbridge/amd/amdmct: Add termination and timing values for C32 sockets
The existing MCT initialization code was largely missing C32 socket- specific configuration data. Add C32 socket-specific timing and ODT values as specified in the BKDG. Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13141 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Timothy Pearson
Martin Roth
parent
19ce16ae69
commit
6aa6eab98b
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@ -1092,6 +1092,152 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
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*/
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}
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}
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} else if (package_type == PT_C3) {
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/* Socket C32 */
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if (pDCTstat->Status & (1 << SB_Registered)) {
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/* RDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 77 */
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if (MaxDimmsInstallable == 1) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x00112222;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x10112222;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x20112222;
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} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
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/* DDR3-1333 - DDR3-1600 */
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calibration_code = 0x30112222;
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}
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if (rank_count_dimm0 == 4) {
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calibration_code &= ~(0xff << 16);
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calibration_code |= 0x22 << 16;
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}
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} else if (MaxDimmsInstallable == 2) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
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rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x00112222;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x10112222;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x20112222;
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} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
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/* DDR3-1333 - DDR3-1600 */
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calibration_code = 0x30112222;
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}
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if ((rank_count_dimm0 == 4) || (rank_count_dimm1 == 4)) {
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calibration_code &= ~(0xff << 16);
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calibration_code |= 0x22 << 16;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
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rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x10222222;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x20222222;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x30222222;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x30222222;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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calibration_code = 0x30222222;
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}
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}
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} else if (MaxDimmsInstallable == 3) {
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/* TODO
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* 3 DIMM/channel support unimplemented
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*/
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}
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} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
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/* LRDIMM */
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/* TODO
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* LRDIMM support unimplemented
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*/
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} else {
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/* UDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
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if (MaxDimmsInstallable == 1) {
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x00112222;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x10112222;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x20112222;
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} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
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/* DDR3-1333 - DDR3-1600 */
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calibration_code = 0x30112222;
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}
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} else if (MaxDimmsInstallable == 2) {
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x00112222;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x10112222;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x20112222;
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} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
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/* DDR3-1333 - DDR3-1600 */
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calibration_code = 0x30112222;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
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rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x10222222;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x20222222;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x30222222;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x30222222;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
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calibration_code = 0x30222222;
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else
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calibration_code = 0x30112222;
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}
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}
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} else if (MaxDimmsInstallable == 3) {
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/* TODO
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* 3 DIMM/channel support unimplemented
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*/
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}
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}
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} else {
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/* TODO
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* Other socket support unimplemented
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@ -1179,7 +1325,161 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
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*/
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} else {
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/* UDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 76 */
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if (MaxDimmsInstallable == 1) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x003b0000;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x003b0000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x00383837;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x00363635;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00353533;
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else
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calibration_code = 0x00003533;
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} else if (MemClkFreq == 0x16) {
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/* DDR3-1866 */
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calibration_code = 0x00333330;
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}
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} else if (MaxDimmsInstallable == 2) {
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x003b0000;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00000000;
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else
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calibration_code = 0x003b0000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x00383837;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x00363635;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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if (rank_count_dimm0 == 1)
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calibration_code = 0x00353533;
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else
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calibration_code = 0x00003533;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
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rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (MemClkFreq == 0x4) {
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/* DDR3-667 */
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calibration_code = 0x00390039;
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} else if (MemClkFreq == 0x6) {
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/* DDR3-800 */
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calibration_code = 0x00390039;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x003a3a3a;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x00003939;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
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calibration_code = 0x00003738;
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}
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}
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} else if (MaxDimmsInstallable == 3) {
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/* TODO
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* 3 DIMM/channel support unimplemented
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*/
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}
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}
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} else if (package_type == PT_C3) {
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/* Socket C32 */
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if (pDCTstat->Status & (1 << SB_Registered)) {
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/* RDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 77 */
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if (MaxDimmsInstallable == 1) {
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
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/* DDR3-667 - DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x003c3c3c;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x003a3a3a;
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} else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) {
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/* DDR3-1600 - DDR3-1866 */
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calibration_code = 0x00393939;
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}
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} else if (MaxDimmsInstallable == 2) {
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
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/* DDR3-667 - DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x00393c39;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x00373a37;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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calibration_code = 0x00363936;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
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/* DDR3-667 - DDR3-800 */
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calibration_code = 0x00000000;
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} else if (MemClkFreq == 0xa) {
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/* DDR3-1066 */
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calibration_code = 0x003a3c3a;
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} else if (MemClkFreq == 0xe) {
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/* DDR3-1333 */
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calibration_code = 0x00383a38;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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calibration_code = 0x00353935;
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}
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}
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} else if (MaxDimmsInstallable == 3) {
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/* TODO
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* 3 DIMM/channel support unimplemented
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*/
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}
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} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
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/* LRDIMM */
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/* TODO
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* LRDIMM support unimplemented
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*/
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} else {
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/* UDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 76 */
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if (MaxDimmsInstallable == 1) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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@ -1310,6 +1610,69 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
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if (MaxDimmsInstallable == 1) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
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|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
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/* DDR3-667 - DDR3-1333 */
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slow_access = 0;
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} else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) {
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/* DDR3-1600 - DDR3-1866 */
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if (rank_count_dimm0 == 1)
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slow_access = 0;
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else
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slow_access = 1;
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}
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} else if (MaxDimmsInstallable == 2) {
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
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|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
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/* DDR3-667 - DDR3-1333 */
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slow_access = 0;
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} else if (MemClkFreq == 0x12) {
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/* DDR3-1600 */
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if (rank_count_dimm0 == 1)
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slow_access = 0;
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else
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slow_access = 1;
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}
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} else if (dimm_count == 2) {
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/* 2 DIMMs detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
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rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
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|| (MemClkFreq == 0xa)) {
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/* DDR3-667 - DDR3-1066 */
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slow_access = 0;
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} else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) {
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/* DDR3-1333 - DDR3-1600 */
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slow_access = 1;
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}
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}
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} else if (MaxDimmsInstallable == 3) {
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/* TODO
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* 3 DIMM/channel support unimplemented
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*/
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}
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}
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} else if (package_type == PT_C3) {
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/* Socket C32 */
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if (pDCTstat->Status & (1 << SB_Registered)) {
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/* RDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 77 */
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slow_access = 0;
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} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
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/* LRDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 78 */
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slow_access = 0;
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} else {
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/* UDIMM */
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/* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 76 */
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if (MaxDimmsInstallable == 1) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
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|| (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
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/* DDR3-667 - DDR3-1333 */
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@ -1433,6 +1796,92 @@ static uint8_t fam15h_odt_tristate_enable_code(struct DCTStatStruc *pDCTstat, ui
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if (MaxDimmsInstallable == 1) {
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (rank_count_dimm0 == 1)
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odt_tristate_code = 0xe;
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else
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odt_tristate_code = 0xa;
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} else if (MaxDimmsInstallable == 2) {
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if (dimm_count == 1) {
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/* 1 DIMM detected */
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rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
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if (rank_count_dimm0 == 1)
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odt_tristate_code = 0xd;
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else
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odt_tristate_code = 0x5;
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} else if (dimm_count == 2) {
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||||
/* 2 DIMMs detected */
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
|
||||
odt_tristate_code = 0xc;
|
||||
else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2))
|
||||
odt_tristate_code = 0x4;
|
||||
else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1))
|
||||
odt_tristate_code = 0x8;
|
||||
else
|
||||
odt_tristate_code = 0x0;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
/* TODO
|
||||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32 */
|
||||
if (pDCTstat->Status & (1 << SB_Registered)) {
|
||||
/* RDIMM */
|
||||
/* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 107 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm0 == 1)
|
||||
odt_tristate_code = 0xe;
|
||||
else
|
||||
odt_tristate_code = 0xa;
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
if (dimm_count == 1) {
|
||||
/* 1 DIMM detected */
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm1 == 1)
|
||||
odt_tristate_code = 0xd;
|
||||
else
|
||||
odt_tristate_code = 0x5;
|
||||
} else if (dimm_count == 2) {
|
||||
/* 2 DIMMs detected */
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
|
||||
odt_tristate_code = 0xc;
|
||||
else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 >= 2))
|
||||
odt_tristate_code = 0x4;
|
||||
else if ((rank_count_dimm0 >= 2) && (rank_count_dimm1 == 1))
|
||||
odt_tristate_code = 0x8;
|
||||
else
|
||||
odt_tristate_code = 0x0;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
/* TODO
|
||||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
|
||||
/* LRDIMM */
|
||||
|
||||
/* TODO
|
||||
* Implement LRDIMM support
|
||||
* See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 108
|
||||
*/
|
||||
} else {
|
||||
/* UDIMM */
|
||||
/* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 106 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm0 == 1)
|
||||
odt_tristate_code = 0xe;
|
||||
else
|
||||
|
|
@ -1542,6 +1991,92 @@ static uint8_t fam15h_cs_tristate_enable_code(struct DCTStatStruc *pDCTstat, uin
|
|||
if (MaxDimmsInstallable == 1) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm0 == 1)
|
||||
cs_tristate_code = 0xfe;
|
||||
else
|
||||
cs_tristate_code = 0xfc;
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
if (dimm_count == 1) {
|
||||
/* 1 DIMM detected */
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm0 == 1)
|
||||
cs_tristate_code = 0xfb;
|
||||
else
|
||||
cs_tristate_code = 0xf3;
|
||||
} else if (dimm_count == 2) {
|
||||
/* 2 DIMMs detected */
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1))
|
||||
cs_tristate_code = 0xfa;
|
||||
else if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 2))
|
||||
cs_tristate_code = 0xf2;
|
||||
else if ((rank_count_dimm0 == 2) && (rank_count_dimm1 == 1))
|
||||
cs_tristate_code = 0xf8;
|
||||
else
|
||||
cs_tristate_code = 0xf0;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
/* TODO
|
||||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32 */
|
||||
if (pDCTstat->Status & (1 << SB_Registered)) {
|
||||
/* RDIMM */
|
||||
/* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 107 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm0 < 4)
|
||||
cs_tristate_code = 0xfc;
|
||||
else
|
||||
cs_tristate_code = 0xcc;
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
if (dimm_count == 1) {
|
||||
/* 1 DIMM detected */
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm1 < 4)
|
||||
cs_tristate_code = 0xf3;
|
||||
else
|
||||
cs_tristate_code = 0x33;
|
||||
} else if (dimm_count == 2) {
|
||||
/* 2 DIMMs detected */
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4))
|
||||
cs_tristate_code = 0xf0;
|
||||
else if ((rank_count_dimm0 < 4) && (rank_count_dimm1 == 4))
|
||||
cs_tristate_code = 0x30;
|
||||
else if ((rank_count_dimm0 == 4) && (rank_count_dimm1 < 4))
|
||||
cs_tristate_code = 0xc0;
|
||||
else
|
||||
cs_tristate_code = 0x0;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
/* TODO
|
||||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
} else if (pDCTstat->Status & (1 << SB_LoadReduced)) {
|
||||
/* LRDIMM */
|
||||
|
||||
/* TODO
|
||||
* Implement LRDIMM support
|
||||
* See Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 108
|
||||
*/
|
||||
} else {
|
||||
/* UDIMM */
|
||||
/* Fam15h BKDG Rev. 3.14 section 2.10.5.10.1 Table 106 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if (rank_count_dimm0 == 1)
|
||||
cs_tristate_code = 0xfe;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -77,6 +77,51 @@ static uint8_t fam15h_rdimm_rc2_ibt_code(struct DCTStatStruc *pDCTstat, uint8_t
|
|||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32 */
|
||||
/* Fam15h BKDG Rev. 3.14 section 2.10.5.7.1.2.1 Table 86 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
|
||||
/* DDR3-667 - DDR3-800 */
|
||||
control_code = 0x1;
|
||||
} else if ((MemClkFreq == 0xa) || (MemClkFreq == 0xe)) {
|
||||
/* DDR3-1066 - DDR3-1333 */
|
||||
if (num_registers == 1) {
|
||||
control_code = 0x0;
|
||||
} else {
|
||||
control_code = 0x1;
|
||||
}
|
||||
} else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) {
|
||||
/* DDR3-1600 - DDR3-1866 */
|
||||
control_code = 0x0;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
if (dimm_count == 1) {
|
||||
/* 1 DIMM detected */
|
||||
if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
|
||||
/* DDR3-667 - DDR3-800 */
|
||||
control_code = 0x1;
|
||||
} else if ((MemClkFreq >= 0xa) && (MemClkFreq <= 0x12)) {
|
||||
/* DDR3-1066 - DDR3-1600 */
|
||||
if (num_registers == 1) {
|
||||
control_code = 0x0;
|
||||
} else {
|
||||
control_code = 0x1;
|
||||
}
|
||||
}
|
||||
} else if (dimm_count == 2) {
|
||||
/* 2 DIMMs detected */
|
||||
if (num_registers == 1) {
|
||||
control_code = 0x1;
|
||||
} else {
|
||||
control_code = 0x8;
|
||||
}
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
/* TODO
|
||||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
} else {
|
||||
/* TODO
|
||||
* Other socket support unimplemented
|
||||
|
|
@ -166,6 +211,13 @@ static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat,
|
|||
val = 0x4;
|
||||
}
|
||||
}
|
||||
else if (package_type == PT_C3) {
|
||||
/* Socket C32 */
|
||||
if (MaxDimmsInstallable == 2) {
|
||||
if (Dimms > 1)
|
||||
val = 0x4;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (CtrlWordNum == 3) {
|
||||
val = (pDCTstat->CtrlWrd3 >> (DimmNum << 2)) & 0xff;
|
||||
|
|
@ -183,6 +235,12 @@ static u32 mct_ControlRC(struct MCTStatStruc *pMCTstat,
|
|||
val = 0x0;
|
||||
}
|
||||
}
|
||||
else if (package_type == PT_C3) {
|
||||
/* Socket C32 */
|
||||
if (MaxDimmsInstallable == 2) {
|
||||
val = 0x0;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (CtrlWordNum == 9) {
|
||||
val = 0xd; /* DBA1, DBA0, DA3 = 0 */
|
||||
|
|
|
|||
|
|
@ -104,6 +104,67 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d
|
|||
} else if (MaxDimmsInstallable == 3) {
|
||||
rank_count_dimm2 = pDCTstat->DimmRanks[(2 * 2) + dct];
|
||||
|
||||
if ((frequency_index == 0xa) || (frequency_index == 0xe)) {
|
||||
/* DDR3-1066 - DDR3-1333 */
|
||||
if (rank_count_dimm2 < 4)
|
||||
term = 0x1;
|
||||
else
|
||||
term = 0x2;
|
||||
} else if (frequency_index == 0x12) {
|
||||
/* DDR3-1600 */
|
||||
term = 0x1;
|
||||
} else {
|
||||
term = 0x2;
|
||||
}
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32: Fam15h BKDG v3.14 Table 60 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
if ((frequency_index == 0x4) || (frequency_index == 0x6)
|
||||
|| (frequency_index == 0xa) || (frequency_index == 0xe)) {
|
||||
/* DDR3-667 - DDR3-1333 */
|
||||
if (rank_count < 3)
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x2;
|
||||
} else {
|
||||
/* DDR3-1600 */
|
||||
term = 0x0;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if ((frequency_index == 0x4) || (frequency_index == 0x6)) {
|
||||
/* DDR3-667 - DDR3-800 */
|
||||
if ((number_of_dimms == 1) && ((rank_count_dimm0 < 4)
|
||||
&& (rank_count_dimm1 < 4)))
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x2;
|
||||
} else if (frequency_index == 0xa) {
|
||||
/* DDR3-1066 */
|
||||
if (number_of_dimms == 1) {
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4))
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x2;
|
||||
} else {
|
||||
term = 0x1;
|
||||
}
|
||||
} else if (frequency_index == 0xe) {
|
||||
/* DDR3-1333 */
|
||||
term = 0x2;
|
||||
} else {
|
||||
/* DDR3-1600 */
|
||||
if (number_of_dimms == 1)
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x1;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
rank_count_dimm2 = pDCTstat->DimmRanks[(2 * 2) + dct];
|
||||
|
||||
if ((frequency_index == 0xa) || (frequency_index == 0xe)) {
|
||||
/* DDR3-1066 - DDR3-1333 */
|
||||
if (rank_count_dimm2 < 4)
|
||||
|
|
@ -151,6 +212,33 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d
|
|||
term = 0x2;
|
||||
}
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32: Fam15h BKDG v3.14 Table 59 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
term = 0x0;
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
if ((number_of_dimms == 2) && (frequency_index == 0x12)) {
|
||||
term = 0x1;
|
||||
} else if (number_of_dimms == 1) {
|
||||
term = 0x0;
|
||||
} else {
|
||||
term = 0x2;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
if (number_of_dimms == 1) {
|
||||
if (frequency_index <= 0xa) {
|
||||
term = 0x2;
|
||||
} else {
|
||||
if (rank_count < 3) {
|
||||
term = 0x1;
|
||||
} else {
|
||||
term = 0x2;
|
||||
}
|
||||
}
|
||||
} else if (number_of_dimms == 2) {
|
||||
term = 0x2;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* TODO
|
||||
* Other sockets unimplemented
|
||||
|
|
@ -302,6 +390,125 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t
|
|||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32: Fam15h BKDG v3.14 Table 60 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
|
||||
if ((frequency_index == 0x4) || (frequency_index == 0x6)) {
|
||||
/* DDR3-667 - DDR3-800 */
|
||||
if (rank_count_dimm0 < 4) {
|
||||
term = 0x2;
|
||||
} else {
|
||||
if (!rank)
|
||||
term = 0x2;
|
||||
else
|
||||
term = 0x0;
|
||||
}
|
||||
} else if (frequency_index == 0xa) {
|
||||
/* DDR3-1066 */
|
||||
term = 0x1;
|
||||
} else if (frequency_index == 0xe) {
|
||||
/* DDR3-1333 */
|
||||
if (rank_count_dimm0 < 4) {
|
||||
term = 0x1;
|
||||
} else {
|
||||
if (!rank)
|
||||
term = 0x3;
|
||||
else
|
||||
term = 0x0;
|
||||
}
|
||||
} else {
|
||||
term = 0x3;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 2) {
|
||||
rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
|
||||
rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
|
||||
|
||||
if ((frequency_index == 0x4) || (frequency_index == 0x6)) {
|
||||
/* DDR3-667 - DDR3-800 */
|
||||
if (number_of_dimms == 1) {
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4))
|
||||
term = 0x2;
|
||||
else if (rank)
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x2;
|
||||
} else {
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) {
|
||||
term = 0x3;
|
||||
} else {
|
||||
if (rank_count_dimm0 == 4) {
|
||||
if (rank_count_dimm1 == 1)
|
||||
term = 0x5;
|
||||
else
|
||||
term = 0x1;
|
||||
} else if (rank_count_dimm1 == 4) {
|
||||
if (rank_count_dimm0 == 1)
|
||||
term = 0x5;
|
||||
else
|
||||
term = 0x1;
|
||||
}
|
||||
if (rank)
|
||||
term = 0x0;
|
||||
}
|
||||
}
|
||||
} else if (frequency_index == 0xa) {
|
||||
/* DDR3-1066 */
|
||||
if (number_of_dimms == 1) {
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4))
|
||||
term = 0x1;
|
||||
else if (rank)
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x1;
|
||||
} else {
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) {
|
||||
term = 0x3;
|
||||
} else {
|
||||
if (rank_count_dimm0 == 4) {
|
||||
if (rank_count_dimm1 == 1)
|
||||
term = 0x5;
|
||||
else
|
||||
term = 0x1;
|
||||
} else if (rank_count_dimm1 == 4) {
|
||||
if (rank_count_dimm0 == 1)
|
||||
term = 0x5;
|
||||
else
|
||||
term = 0x1;
|
||||
}
|
||||
if (rank)
|
||||
term = 0x0;
|
||||
}
|
||||
}
|
||||
} else if (frequency_index == 0xe) {
|
||||
/* DDR3-1333 */
|
||||
if (number_of_dimms == 1) {
|
||||
if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4))
|
||||
term = 0x1;
|
||||
else if (rank)
|
||||
term = 0x0;
|
||||
else
|
||||
term = 0x3;
|
||||
} else {
|
||||
term = 0x5;
|
||||
}
|
||||
} else {
|
||||
/* DDR3-1600 */
|
||||
if (number_of_dimms == 1)
|
||||
term = 0x3;
|
||||
else
|
||||
term = 0x4;
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
/* TODO
|
||||
* 3 DIMM/channel support unimplemented
|
||||
*/
|
||||
}
|
||||
} else {
|
||||
/* TODO
|
||||
* Other sockets unimplemented
|
||||
*/
|
||||
}
|
||||
} else {
|
||||
/* UDIMM */
|
||||
|
|
@ -352,6 +559,53 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t
|
|||
}
|
||||
}
|
||||
}
|
||||
} else if (package_type == PT_C3) {
|
||||
/* Socket C32: Fam15h BKDG v3.14 Table 62 */
|
||||
if (MaxDimmsInstallable == 1) {
|
||||
if ((frequency_index == 0x4) || (frequency_index == 0x6))
|
||||
term = 0x2;
|
||||
else if ((frequency_index == 0xa) || (frequency_index == 0xe))
|
||||
term = 0x1;
|
||||
else
|
||||
term = 0x3;
|
||||
}
|
||||
if (MaxDimmsInstallable == 2) {
|
||||
if (number_of_dimms == 1) {
|
||||
if (frequency_index <= 0x6) {
|
||||
term = 0x2;
|
||||
} else if (frequency_index <= 0xe) {
|
||||
term = 0x1;
|
||||
} else {
|
||||
term = 0x3;
|
||||
}
|
||||
} else {
|
||||
if (frequency_index <= 0xa) {
|
||||
term = 0x3;
|
||||
} else if (frequency_index <= 0xe) {
|
||||
term = 0x5;
|
||||
} else {
|
||||
term = 0x4;
|
||||
}
|
||||
}
|
||||
} else if (MaxDimmsInstallable == 3) {
|
||||
if (number_of_dimms == 1) {
|
||||
term = 0x0;
|
||||
} else if (number_of_dimms == 2) {
|
||||
if (frequency_index <= 0xa) {
|
||||
if (rank == 1) {
|
||||
term = 0x0;
|
||||
} else {
|
||||
term = 0x3;
|
||||
}
|
||||
} else if (frequency_index <= 0xe) {
|
||||
if (rank == 1) {
|
||||
term = 0x0;
|
||||
} else {
|
||||
term = 0x5;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* TODO
|
||||
* Other sockets unimplemented
|
||||
|
|
|
|||
Loading…
Reference in New Issue