mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb

For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.

BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.

Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/deltaur/variants/baseboard/devicetree.cb

@@ -1,7 +1,5 @@
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -79,8 +79,6 @@ end
 
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -1,7 +1,5 @@
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -1,7 +1,5 @@
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on end
-
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route. i.e. If this route changes then the affected GPE

src/soc/intel/tigerlake/chipset.cb

@@ -1,4 +1,6 @@
 chip soc/intel/tigerlake
+
+	device cpu_cluster 0 on end
 	device domain 0 on
 		device gpio 0 alias pch_gpio on end
 		device pci 00.0 alias system_agent on end