mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID

coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.

As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.

BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.

Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/deltaur/variants/baseboard/devicetree.cb

@@ -1,8 +1,6 @@
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
+	device cpu_cluster 0 on end
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/google/volteer/variants/baseboard/devicetree.cb

@@ -79,9 +79,7 @@ end
 
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
+	device cpu_cluster 0 on end
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb

@@ -1,8 +1,6 @@
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
+	device cpu_cluster 0 on end
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this

src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb

@@ -1,8 +1,6 @@
 chip soc/intel/tigerlake
 
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
+	device cpu_cluster 0 on end
 
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this