google/chell: Convert to a variant of glados
Convert chell to a variant of glados Skylake reference board:
- add chell-specific DPTF, EC config, USB port defs, GPIO config,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add romstage handler to turn on keyboard backlight for boards
so equipped
- remove existing chell board/directory
Test: build/boot google/chell, verify functionality unchanged
from pre-variant configuration
Change-Id: I7dfbafe3afcab7cee7bcb2bf91c6733c07b409c4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Matt DeVillier
Martin Roth
parent
0b9cfe60b2
commit
39f3c7e184
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@ -1,71 +0,0 @@
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if BOARD_GOOGLE_CHELL
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_NAU8825
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_LPC
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select EC_GOOGLE_CHROMEEC_MEC
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select EC_GOOGLE_CHROMEEC_PD
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select INTEL_GMA_HAVE_VBT
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MAINBOARD_HAS_TPM1
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select SOC_INTEL_SKYLAKE
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select SYSTEM_TYPE_LAPTOP
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config VBOOT
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select EC_GOOGLE_CHROMEEC_SWITCHES
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select VBOOT_LID_SWITCH
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAINBOARD_DIR
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string
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default "google/chell"
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config MAINBOARD_PART_NUMBER
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string
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default "Chell"
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config MAINBOARD_FAMILY
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string
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default "Google_Glados"
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config MAX_CPUS
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int
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default 8
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config TPM_PIRQ
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hex
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default 0x18 # GPP_E0_IRQ
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config INCLUDE_NHLT_BLOBS
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bool "Include blobs for audio."
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select NHLT_DMIC_2CH
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select NHLT_NAU88L25
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select NHLT_SSM4567
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config EC_GOOGLE_CHROMEEC_BOARDNAME
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string
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default "chell"
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config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
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string
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default "chell_pd"
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config GBB_HWID
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string
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depends on CHROMEOS
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default "CHELL TEST 6297"
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endif
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@ -1,2 +0,0 @@
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config BOARD_GOOGLE_CHELL
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bool "Chell (HP Chromebook 13 G1)"
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@ -1,33 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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bootblock-y += bootblock_mainboard.c
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romstage-y += pei_data.c
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bootblock-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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romstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
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ramstage-y += mainboard.c
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ramstage-y += pei_data.c
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ramstage-y += ramstage.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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@ -1,31 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* mainboard configuration */
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#include "../ec.h"
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#include "../gpio.h"
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/* Enable EC backed Keyboard Backlight in ACPI */
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#define EC_ENABLE_KEYBOARD_BACKLIGHT
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/* Enable EC backed PD MCU device in ACPI */
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#define EC_ENABLE_PD_MCU_DEVICE
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/* Enable LID switch and provide wake pin for EC */
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#define EC_ENABLE_LID_SWITCH
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#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
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/* ACPI code for EC functions */
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#include <ec/google/chromeec/acpi/ec.asl>
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@ -1,24 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* mainboard configuration */
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#include "../ec.h"
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#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
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#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
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#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
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/* ACPI code for EC SuperIO functions */
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#include <ec/google/chromeec/acpi/superio.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include "gpio.h"
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static void early_config_gpio(void)
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{
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/* This is a hack for FSP because it does things in MemoryInit()
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* which it shouldn't do. We have to prepare certain gpios here
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* because of the brokenness in FSP. */
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <rules.h>
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#include <gpio.h>
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#include <soc/gpio.h>
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#include <string.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "gpio.h"
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#if ENV_RAMSTAGE
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#include <boot/coreboot_tables.h>
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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struct lb_gpio chromeos_gpios[] = {
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{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
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{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
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{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
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{-1, ACTIVE_HIGH, 0, "power"},
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{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
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{GPIO_EC_IN_RW, ACTIVE_HIGH,
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gpio_get(GPIO_EC_IN_RW), "EC in RW"},
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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}
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#endif /* ENV_RAMSTAGE */
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int get_write_protect_state(void)
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{
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/* Read PCH_WP GPIO. */
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return gpio_get(GPIO_PCH_WP);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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FLASH@0xff000000 0x1000000 {
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SI_ALL@0x0 0x200000 {
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SI_DESC@0x0 0x1000
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SI_ME@0x1000 0x1ff000
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}
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SI_BIOS@0x200000 0xe00000 {
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RW_SECTION_A@0x0 0x3f0000 {
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VBLOCK_A@0x0 0x10000
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FW_MAIN_A(CBFS)@0x10000 0x3dffc0
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RW_FWID_A@0x3effc0 0x40
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}
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RW_SECTION_B@0x3f0000 0x3f0000 {
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VBLOCK_B@0x0 0x10000
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FW_MAIN_B(CBFS)@0x10000 0x3dffc0
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RW_FWID_B@0x3effc0 0x40
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}
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RW_MRC_CACHE@0x7e0000 0x10000
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RW_ELOG@0x7f0000 0x4000
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RW_SHARED@0x7f4000 0x4000 {
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SHARED_DATA@0x0 0x2000
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VBLOCK_DEV@0x2000 0x2000
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}
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RW_VPD@0x7f8000 0x2000
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RW_NVRAM@0x7fa000 0x6000
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RW_LEGACY(CBFS)@0x800000 0x200000
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WP_RO@0xa00000 0x400000 {
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RO_VPD@0x0 0x4000
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RO_UNUSED@0x4000 0xc000
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RO_SECTION@0x10000 0x3f0000 {
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FMAP@0x0 0x800
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RO_FRID@0x800 0x40
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RO_FRID_PAD@0x840 0x7c0
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GBB@0x1000 0xef000
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COREBOOT(CBFS)@0xf0000 0x300000
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}
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}
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}
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}
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@ -1,125 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2015 Intel Corporation
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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# -----------------------------------------------------------------
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# Status Register A
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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# -----------------------------------------------------------------
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# Status Register B
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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|
||||||
409 2 e 7 power_on_after_fail
|
|
||||||
#411 5 r 0 unused
|
|
||||||
|
|
||||||
# coreboot config options: bootloader
|
|
||||||
#Used by ChromeOS:
|
|
||||||
416 128 r 0 vbnv
|
|
||||||
#544 440 r 0 unused
|
|
||||||
|
|
||||||
# SandyBridge MRC Scrambler Seed values
|
|
||||||
896 32 r 0 mrc_scrambler_seed
|
|
||||||
928 32 r 0 mrc_scrambler_seed_s3
|
|
||||||
|
|
||||||
# coreboot config options: check sums
|
|
||||||
984 16 h 0 check_sum
|
|
||||||
#1000 24 r 0 amd_reserved
|
|
||||||
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
|
|
||||||
enumerations
|
|
||||||
|
|
||||||
#ID value text
|
|
||||||
1 0 Disable
|
|
||||||
1 1 Enable
|
|
||||||
2 0 Enable
|
|
||||||
2 1 Disable
|
|
||||||
4 0 Fallback
|
|
||||||
4 1 Normal
|
|
||||||
6 0 Emergency
|
|
||||||
6 1 Alert
|
|
||||||
6 2 Critical
|
|
||||||
6 3 Error
|
|
||||||
6 4 Warning
|
|
||||||
6 5 Notice
|
|
||||||
6 6 Info
|
|
||||||
6 7 Debug
|
|
||||||
6 8 Spew
|
|
||||||
7 0 Disable
|
|
||||||
7 1 Enable
|
|
||||||
7 2 Keep
|
|
||||||
# -----------------------------------------------------------------
|
|
||||||
checksums
|
|
||||||
|
|
||||||
checksum 392 415 984
|
|
||||||
|
|
@ -1,55 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
DefinitionBlock(
|
|
||||||
"dsdt.aml",
|
|
||||||
"DSDT",
|
|
||||||
0x05, // DSDT revision: ACPI v5.0
|
|
||||||
"COREv4", // OEM id
|
|
||||||
"COREBOOT", // OEM table id
|
|
||||||
0x20110725 // OEM revision
|
|
||||||
)
|
|
||||||
{
|
|
||||||
// Some generic macros
|
|
||||||
#include <soc/intel/skylake/acpi/platform.asl>
|
|
||||||
|
|
||||||
// global NVS and variables
|
|
||||||
#include <soc/intel/skylake/acpi/globalnvs.asl>
|
|
||||||
|
|
||||||
// CPU
|
|
||||||
#include <soc/intel/skylake/acpi/cpu.asl>
|
|
||||||
|
|
||||||
Scope (\_SB) {
|
|
||||||
Device (PCI0)
|
|
||||||
{
|
|
||||||
#include <soc/intel/skylake/acpi/systemagent.asl>
|
|
||||||
#include <soc/intel/skylake/acpi/pch.asl>
|
|
||||||
}
|
|
||||||
|
|
||||||
// Dynamic Platform Thermal Framework
|
|
||||||
#include "acpi/dptf.asl"
|
|
||||||
}
|
|
||||||
|
|
||||||
// Chrome OS specific
|
|
||||||
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
|
|
||||||
|
|
||||||
// Chipset specific sleep states
|
|
||||||
#include <soc/intel/skylake/acpi/sleepstates.asl>
|
|
||||||
|
|
||||||
// Mainboard specific
|
|
||||||
#include "acpi/mainboard.asl"
|
|
||||||
}
|
|
||||||
|
|
@ -1,34 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <ec/google/chromeec/ec.h>
|
|
||||||
#include "ec.h"
|
|
||||||
|
|
||||||
void mainboard_ec_init(void)
|
|
||||||
{
|
|
||||||
const struct google_chromeec_event_info info = {
|
|
||||||
.log_events = MAINBOARD_EC_LOG_EVENTS,
|
|
||||||
.sci_events = MAINBOARD_EC_SCI_EVENTS,
|
|
||||||
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
|
|
||||||
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
|
|
||||||
};
|
|
||||||
|
|
||||||
printk(BIOS_DEBUG, "mainboard: EC init\n");
|
|
||||||
|
|
||||||
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
|
|
||||||
}
|
|
||||||
|
|
@ -1,58 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MAINBOARD_EC_H
|
|
||||||
#define MAINBOARD_EC_H
|
|
||||||
|
|
||||||
#include <ec/ec.h>
|
|
||||||
#include <ec/google/chromeec/ec_commands.h>
|
|
||||||
|
|
||||||
#define MAINBOARD_EC_SCI_EVENTS \
|
|
||||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
|
|
||||||
|
|
||||||
#define MAINBOARD_EC_SMI_EVENTS \
|
|
||||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
|
|
||||||
|
|
||||||
/* EC can wake from S5 with lid or power button */
|
|
||||||
#define MAINBOARD_EC_S5_WAKE_EVENTS \
|
|
||||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
|
|
||||||
|
|
||||||
/* EC can wake from S3 with lid or power button or key press */
|
|
||||||
#define MAINBOARD_EC_S3_WAKE_EVENTS \
|
|
||||||
(MAINBOARD_EC_S5_WAKE_EVENTS |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
|
|
||||||
|
|
||||||
/* Log EC wake events plus EC shutdown events */
|
|
||||||
#define MAINBOARD_EC_LOG_EVENTS \
|
|
||||||
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
|
|
||||||
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,78 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <device/device.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <soc/nhlt.h>
|
|
||||||
#include <vendorcode/google/chromeos/chromeos.h>
|
|
||||||
#include "ec.h"
|
|
||||||
|
|
||||||
static void mainboard_init(struct device *dev)
|
|
||||||
{
|
|
||||||
mainboard_ec_init();
|
|
||||||
}
|
|
||||||
|
|
||||||
static unsigned long mainboard_write_acpi_tables(
|
|
||||||
struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
|
|
||||||
{
|
|
||||||
uintptr_t start_addr;
|
|
||||||
uintptr_t end_addr;
|
|
||||||
struct nhlt *nhlt;
|
|
||||||
|
|
||||||
start_addr = current;
|
|
||||||
|
|
||||||
nhlt = nhlt_init();
|
|
||||||
|
|
||||||
if (nhlt == NULL)
|
|
||||||
return start_addr;
|
|
||||||
|
|
||||||
/* 2 Channel DMIC array. */
|
|
||||||
if (nhlt_soc_add_dmic_array(nhlt, 2))
|
|
||||||
printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
|
|
||||||
|
|
||||||
/* ADI Smart Amps for left and right. */
|
|
||||||
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
|
|
||||||
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
|
|
||||||
|
|
||||||
/* NAU88l25 Headset codec. */
|
|
||||||
if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
|
|
||||||
printk(BIOS_ERR, "Couldn't add headset codec.\n");
|
|
||||||
|
|
||||||
end_addr = nhlt_soc_serialize(nhlt, start_addr);
|
|
||||||
|
|
||||||
if (end_addr != start_addr)
|
|
||||||
acpi_add_table(rsdp, (void *)start_addr);
|
|
||||||
|
|
||||||
return end_addr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* mainboard_enable is executed as first thing after
|
|
||||||
* enumerate_buses().
|
|
||||||
*/
|
|
||||||
static void mainboard_enable(struct device *dev)
|
|
||||||
{
|
|
||||||
dev->ops->init = mainboard_init;
|
|
||||||
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
|
|
||||||
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
|
|
||||||
}
|
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
|
||||||
.enable_dev = mainboard_enable,
|
|
||||||
};
|
|
||||||
|
|
@ -1,25 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <soc/ramstage.h>
|
|
||||||
#include "gpio.h"
|
|
||||||
|
|
||||||
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
|
|
||||||
{
|
|
||||||
/* Configure pads prior to SiliconInit() in case there's any
|
|
||||||
* dependencies during hardware initialization. */
|
|
||||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
|
||||||
}
|
|
||||||
|
|
@ -1,62 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007-2010 coresystems GmbH
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <string.h>
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <ec/google/chromeec/ec.h>
|
|
||||||
#include <soc/pei_data.h>
|
|
||||||
#include <soc/pei_wrapper.h>
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include "spd/spd.h"
|
|
||||||
|
|
||||||
void mainboard_romstage_entry(struct romstage_params *params)
|
|
||||||
{
|
|
||||||
/* Turn on keyboard backlight to indicate we are booting */
|
|
||||||
if (params->power_state->prev_sleep_state != ACPI_S3)
|
|
||||||
google_chromeec_kbbacklight(25);
|
|
||||||
|
|
||||||
/* Fill out PEI DATA */
|
|
||||||
mainboard_fill_pei_data(params->pei_data);
|
|
||||||
mainboard_fill_spd_data(params->pei_data);
|
|
||||||
/* Initialize memory */
|
|
||||||
romstage_common(params);
|
|
||||||
}
|
|
||||||
|
|
||||||
void mainboard_memory_init_params(struct romstage_params *params,
|
|
||||||
MEMORY_INIT_UPD *memory_params)
|
|
||||||
{
|
|
||||||
if (params->pei_data->spd_data[0][0][0] != 0) {
|
|
||||||
memory_params->MemorySpdPtr00 =
|
|
||||||
(UINT32)(params->pei_data->spd_data[0][0]);
|
|
||||||
memory_params->MemorySpdPtr10 =
|
|
||||||
(UINT32)(params->pei_data->spd_data[1][0]);
|
|
||||||
}
|
|
||||||
memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],
|
|
||||||
sizeof(params->pei_data->dq_map[0]));
|
|
||||||
memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],
|
|
||||||
sizeof(params->pei_data->dq_map[1]));
|
|
||||||
memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],
|
|
||||||
sizeof(params->pei_data->dqs_map[0]));
|
|
||||||
memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],
|
|
||||||
sizeof(params->pei_data->dqs_map[1]));
|
|
||||||
memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,
|
|
||||||
sizeof(params->pei_data->RcompResistor));
|
|
||||||
memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,
|
|
||||||
sizeof(params->pei_data->RcompTarget));
|
|
||||||
memory_params->MemorySpdDataLen = SPD_LEN;
|
|
||||||
memory_params->DqPinsInterleaved = FALSE;
|
|
||||||
}
|
|
||||||
|
|
@ -1,89 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2008-2009 coresystems GmbH
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/acpi.h>
|
|
||||||
#include <arch/io.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <cpu/x86/smm.h>
|
|
||||||
#include <elog.h>
|
|
||||||
#include <ec/google/chromeec/smm.h>
|
|
||||||
#include <gpio.h>
|
|
||||||
#include <soc/iomap.h>
|
|
||||||
#include <soc/nvs.h>
|
|
||||||
#include <soc/pm.h>
|
|
||||||
#include <soc/smm.h>
|
|
||||||
#include "ec.h"
|
|
||||||
#include "gpio.h"
|
|
||||||
|
|
||||||
int mainboard_io_trap_handler(int smif)
|
|
||||||
{
|
|
||||||
switch (smif) {
|
|
||||||
case 0x99:
|
|
||||||
printk(BIOS_DEBUG, "Sample\n");
|
|
||||||
smm_get_gnvs()->smif = 0;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* On success, the IO Trap Handler returns 0
|
|
||||||
* On failure, the IO Trap Handler returns a value != 0
|
|
||||||
*
|
|
||||||
* For now, we force the return value to 0 and log all traps to
|
|
||||||
* see what's going on.
|
|
||||||
*/
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
|
|
||||||
{
|
|
||||||
if (gpi_status_get(sts, EC_SMI_GPI))
|
|
||||||
chromeec_smi_process_events();
|
|
||||||
}
|
|
||||||
|
|
||||||
static void mainboard_gpio_smi_sleep(u8 slp_typ)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/* Power down the rails on any sleep type. */
|
|
||||||
gpio_t active_high_signals[] = {
|
|
||||||
EN_PP3300_KEPLER,
|
|
||||||
EN_PP3300_DX_TOUCH,
|
|
||||||
EN_PP3300_DX_EMMC,
|
|
||||||
EN_PP1800_DX_EMMC,
|
|
||||||
EN_PP3300_DX_CAM,
|
|
||||||
};
|
|
||||||
|
|
||||||
for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
|
|
||||||
gpio_set(active_high_signals[i], 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
void mainboard_smi_sleep(u8 slp_typ)
|
|
||||||
{
|
|
||||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
|
||||||
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
|
|
||||||
MAINBOARD_EC_S5_WAKE_EVENTS);
|
|
||||||
|
|
||||||
mainboard_gpio_smi_sleep(slp_typ);
|
|
||||||
}
|
|
||||||
|
|
||||||
int mainboard_smi_apmc(u8 apmc)
|
|
||||||
{
|
|
||||||
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
|
|
||||||
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
|
|
||||||
MAINBOARD_EC_SMI_EVENTS);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,16 +0,0 @@
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
|
|
@ -1,16 +0,0 @@
|
||||||
91 20 F1 03 04 12 05 0A 03 11 01 08 09 00 50 05
|
|
||||||
78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
|
|
||||||
00 80 ca fa 00 00 00 A8 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00
|
|
||||||
4B 34 45 36 45 33 30 34 45 45 2D 45 47 43 46 20
|
|
||||||
20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
||||||
|
|
@ -1,123 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/byteorder.h>
|
|
||||||
#include <cbfs.h>
|
|
||||||
#include <console/console.h>
|
|
||||||
#include <gpio.h>
|
|
||||||
#include <soc/gpio.h>
|
|
||||||
#include <soc/pei_data.h>
|
|
||||||
#include <soc/romstage.h>
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
#include "../gpio.h"
|
|
||||||
#include "spd.h"
|
|
||||||
|
|
||||||
static void mainboard_print_spd_info(uint8_t spd[])
|
|
||||||
{
|
|
||||||
const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
|
|
||||||
const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
|
|
||||||
const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
|
|
||||||
const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
|
|
||||||
const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
|
|
||||||
const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
|
|
||||||
const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
|
|
||||||
char spd_name[SPD_PART_LEN+1] = { 0 };
|
|
||||||
|
|
||||||
int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
|
|
||||||
int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
|
|
||||||
int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
|
|
||||||
int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
|
|
||||||
int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
|
|
||||||
int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
|
|
||||||
int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
|
|
||||||
|
|
||||||
/* Module type */
|
|
||||||
printk(BIOS_INFO, "SPD: module type is ");
|
|
||||||
switch (spd[SPD_DRAM_TYPE]) {
|
|
||||||
case SPD_DRAM_DDR3:
|
|
||||||
printk(BIOS_INFO, "DDR3\n");
|
|
||||||
break;
|
|
||||||
case SPD_DRAM_LPDDR3:
|
|
||||||
printk(BIOS_INFO, "LPDDR3\n");
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Module Part Number */
|
|
||||||
memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
|
|
||||||
spd_name[SPD_PART_LEN] = 0;
|
|
||||||
printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
|
|
||||||
|
|
||||||
printk(BIOS_INFO,
|
|
||||||
"SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
|
|
||||||
banks, ranks, rows, cols, capmb);
|
|
||||||
printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
|
|
||||||
devw, busw);
|
|
||||||
|
|
||||||
if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
|
|
||||||
/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
|
|
||||||
printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
|
|
||||||
capmb / 8 * busw / devw * ranks);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Copy SPD data for on-board memory */
|
|
||||||
void mainboard_fill_spd_data(struct pei_data *pei_data)
|
|
||||||
{
|
|
||||||
char *spd_file;
|
|
||||||
size_t spd_file_len;
|
|
||||||
int spd_index;
|
|
||||||
|
|
||||||
gpio_t spd_gpios[] = {
|
|
||||||
GPIO_MEM_CONFIG_0,
|
|
||||||
GPIO_MEM_CONFIG_1,
|
|
||||||
GPIO_MEM_CONFIG_2,
|
|
||||||
GPIO_MEM_CONFIG_3,
|
|
||||||
};
|
|
||||||
|
|
||||||
spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
|
||||||
printk(BIOS_INFO, "SPD index %d\n", spd_index);
|
|
||||||
|
|
||||||
/* Load SPD data from CBFS */
|
|
||||||
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
|
|
||||||
&spd_file_len);
|
|
||||||
if (!spd_file)
|
|
||||||
die("SPD data not found.");
|
|
||||||
|
|
||||||
/* make sure we have at least one SPD in the file. */
|
|
||||||
if (spd_file_len < SPD_LEN)
|
|
||||||
die("Missing SPD data.");
|
|
||||||
|
|
||||||
/* Make sure we did not overrun the buffer */
|
|
||||||
if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
|
|
||||||
printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n");
|
|
||||||
spd_index = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Assume same memory in both channels */
|
|
||||||
spd_index *= SPD_LEN;
|
|
||||||
memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN);
|
|
||||||
memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN);
|
|
||||||
|
|
||||||
/* Make sure a valid SPD was found */
|
|
||||||
if (pei_data->spd_data[0][0][0] == 0)
|
|
||||||
die("Invalid SPD data.");
|
|
||||||
|
|
||||||
mainboard_print_spd_info(pei_data->spd_data[0][0]);
|
|
||||||
}
|
|
||||||
|
|
@ -1,33 +0,0 @@
|
||||||
/*
|
|
||||||
* This file is part of the coreboot project.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2015 Google Inc.
|
|
||||||
* Copyright (C) 2015 Intel Corporation
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License as published by
|
|
||||||
* the Free Software Foundation; version 2 of the License.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef MAINBOARD_SPD_H
|
|
||||||
#define MAINBOARD_SPD_H
|
|
||||||
|
|
||||||
#define SPD_LEN 256
|
|
||||||
|
|
||||||
#define SPD_DRAM_TYPE 2
|
|
||||||
#define SPD_DRAM_DDR3 0x0b
|
|
||||||
#define SPD_DRAM_LPDDR3 0xf1
|
|
||||||
#define SPD_DENSITY_BANKS 4
|
|
||||||
#define SPD_ADDRESSING 5
|
|
||||||
#define SPD_ORGANIZATION 7
|
|
||||||
#define SPD_BUS_DEV_WIDTH 8
|
|
||||||
#define SPD_PART_OFF 128
|
|
||||||
#define SPD_PART_LEN 18
|
|
||||||
#define SPD_MANU_OFF 148
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -13,6 +13,7 @@ config BOARD_GOOGLE_BASEBOARD_GLADOS
|
||||||
select HAVE_ACPI_TABLES
|
select HAVE_ACPI_TABLES
|
||||||
select HAVE_OPTION_TABLE
|
select HAVE_OPTION_TABLE
|
||||||
select HAVE_SMI_HANDLER
|
select HAVE_SMI_HANDLER
|
||||||
|
select INTEL_GMA_HAVE_VBT if !BOARD_GOOGLE_GLADOS
|
||||||
select MAINBOARD_HAS_CHROMEOS
|
select MAINBOARD_HAS_CHROMEOS
|
||||||
select MAINBOARD_HAS_LPC_TPM
|
select MAINBOARD_HAS_LPC_TPM
|
||||||
select MAINBOARD_HAS_TPM1
|
select MAINBOARD_HAS_TPM1
|
||||||
|
|
@ -35,6 +36,7 @@ config MAINBOARD_DIR
|
||||||
|
|
||||||
config MAINBOARD_PART_NUMBER
|
config MAINBOARD_PART_NUMBER
|
||||||
string
|
string
|
||||||
|
default "Chell" if BOARD_GOOGLE_CHELL
|
||||||
default "Glados" if BOARD_GOOGLE_GLADOS
|
default "Glados" if BOARD_GOOGLE_GLADOS
|
||||||
|
|
||||||
config MAINBOARD_FAMILY
|
config MAINBOARD_FAMILY
|
||||||
|
|
@ -43,10 +45,12 @@ config MAINBOARD_FAMILY
|
||||||
|
|
||||||
config VARIANT_DIR
|
config VARIANT_DIR
|
||||||
string
|
string
|
||||||
|
default "chell" if BOARD_GOOGLE_CHELL
|
||||||
default "glados" if BOARD_GOOGLE_GLADOS
|
default "glados" if BOARD_GOOGLE_GLADOS
|
||||||
|
|
||||||
config DEVICETREE
|
config DEVICETREE
|
||||||
string
|
string
|
||||||
|
default "variants/chell/devicetree.cb" if BOARD_GOOGLE_CHELL
|
||||||
default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
|
default "variants/glados/devicetree.cb" if BOARD_GOOGLE_GLADOS
|
||||||
|
|
||||||
config MAX_CPUS
|
config MAX_CPUS
|
||||||
|
|
@ -64,14 +68,17 @@ config INCLUDE_NHLT_BLOBS
|
||||||
|
|
||||||
config EC_GOOGLE_CHROMEEC_BOARDNAME
|
config EC_GOOGLE_CHROMEEC_BOARDNAME
|
||||||
string
|
string
|
||||||
|
default "chell" if BOARD_GOOGLE_CHELL
|
||||||
default "glados" if BOARD_GOOGLE_GLADOS
|
default "glados" if BOARD_GOOGLE_GLADOS
|
||||||
|
|
||||||
config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
|
config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
|
||||||
string
|
string
|
||||||
|
default "chell_pd" if BOARD_GOOGLE_CHELL
|
||||||
default "glados_pd" if BOARD_GOOGLE_GLADOS
|
default "glados_pd" if BOARD_GOOGLE_GLADOS
|
||||||
|
|
||||||
config GBB_HWID
|
config GBB_HWID
|
||||||
string
|
string
|
||||||
depends on CHROMEOS
|
depends on CHROMEOS
|
||||||
|
default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL
|
||||||
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
|
default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS
|
||||||
endif
|
endif
|
||||||
|
|
|
||||||
|
|
@ -1,5 +1,10 @@
|
||||||
comment "Glados"
|
comment "Glados"
|
||||||
|
|
||||||
|
config BOARD_GOOGLE_CHELL
|
||||||
|
bool "-> Chell (HP Chromebook 13 G1)"
|
||||||
|
select BOARD_GOOGLE_BASEBOARD_GLADOS
|
||||||
|
select NHLT_SSM4567 if INCLUDE_NHLT_BLOBS
|
||||||
|
|
||||||
config BOARD_GOOGLE_GLADOS
|
config BOARD_GOOGLE_GLADOS
|
||||||
bool "-> Glados Skylake Reference Board"
|
bool "-> Glados Skylake Reference Board"
|
||||||
select BOARD_GOOGLE_BASEBOARD_GLADOS
|
select BOARD_GOOGLE_BASEBOARD_GLADOS
|
||||||
|
|
|
||||||
|
|
@ -22,10 +22,16 @@
|
||||||
#include <soc/pei_wrapper.h>
|
#include <soc/pei_wrapper.h>
|
||||||
#include <soc/romstage.h>
|
#include <soc/romstage.h>
|
||||||
#include "spd/spd.h"
|
#include "spd/spd.h"
|
||||||
|
#include <variant/ec.h>
|
||||||
#include <variant/gpio.h>
|
#include <variant/gpio.h>
|
||||||
|
|
||||||
void mainboard_romstage_entry(struct romstage_params *params)
|
void mainboard_romstage_entry(struct romstage_params *params)
|
||||||
{
|
{
|
||||||
|
#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT
|
||||||
|
/* Turn on keyboard backlight to indicate we are booting */
|
||||||
|
if (params->power_state->prev_sleep_state != ACPI_S3)
|
||||||
|
google_chromeec_kbbacklight(25);
|
||||||
|
#endif
|
||||||
/* Get SPD index */
|
/* Get SPD index */
|
||||||
gpio_t spd_gpios[] = {
|
gpio_t spd_gpios[] = {
|
||||||
GPIO_MEM_CONFIG_0,
|
GPIO_MEM_CONFIG_0,
|
||||||
|
|
|
||||||
|
|
@ -14,7 +14,9 @@
|
||||||
## GNU General Public License for more details.
|
## GNU General Public License for more details.
|
||||||
##
|
##
|
||||||
|
|
||||||
romstage-y += spd.c
|
romstage-y += variant.c
|
||||||
|
ramstage-y += variant.c
|
||||||
|
smm-y += variant.c
|
||||||
|
|
||||||
SPD_BIN = $(obj)/spd.bin
|
SPD_BIN = $(obj)/spd.bin
|
||||||
|
|
||||||
|
|
@ -1,5 +1,5 @@
|
||||||
Vendor name: Google
|
Vendor name: Google
|
||||||
Board name: Chell Skylake Reference Board
|
Board name: Chell (HP Chromebook 13 G1)
|
||||||
Category: laptop
|
Category: laptop
|
||||||
ROM protocol: SPI
|
ROM protocol: SPI
|
||||||
ROM socketed: n
|
ROM socketed: n
|
||||||
|
|
@ -89,6 +89,3 @@ Name (MPPC, Package ()
|
||||||
1000 /* StepSize */
|
1000 /* StepSize */
|
||||||
}
|
}
|
||||||
})
|
})
|
||||||
|
|
||||||
/* Include DPTF */
|
|
||||||
#include <soc/intel/skylake/acpi/dptf/dptf.asl>
|
|
||||||
|
|
@ -13,15 +13,5 @@
|
||||||
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "../gpio.h"
|
/* Enable EC backed Keyboard Backlight in ACPI */
|
||||||
|
#define EC_ENABLE_KEYBOARD_BACKLIGHT
|
||||||
Scope (\_SB)
|
|
||||||
{
|
|
||||||
Device (PWRB)
|
|
||||||
{
|
|
||||||
Name (_HID, EisaId ("PNP0C0C"))
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* USB port entries */
|
|
||||||
#include "usb.asl"
|
|
||||||
|
|
@ -14,10 +14,13 @@
|
||||||
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <baseboard/variant.h>
|
||||||
|
#include <gpio.h>
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
#include <string.h>
|
#include <string.h>
|
||||||
#include <soc/pei_data.h>
|
#include <soc/pei_data.h>
|
||||||
#include <soc/pei_wrapper.h>
|
#include <soc/pei_wrapper.h>
|
||||||
|
#include <variant/gpio.h>
|
||||||
|
|
||||||
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||||
{
|
{
|
||||||
|
|
@ -45,3 +48,20 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||||
memcpy(pei_data->RcompTarget, RcompTarget,
|
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||||
sizeof(RcompTarget));
|
sizeof(RcompTarget));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void mainboard_gpio_smi_sleep(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* Power down the rails on any sleep type. */
|
||||||
|
gpio_t active_high_signals[] = {
|
||||||
|
EN_PP3300_KEPLER,
|
||||||
|
EN_PP3300_DX_TOUCH,
|
||||||
|
EN_PP3300_DX_EMMC,
|
||||||
|
EN_PP1800_DX_EMMC,
|
||||||
|
EN_PP3300_DX_CAM,
|
||||||
|
};
|
||||||
|
|
||||||
|
for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
|
||||||
|
gpio_set(active_high_signals[i], 0);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue