x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]
This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: I3233ba1747dcf5ad05b2ad771a86e3936f655d1c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Felix Held
parent
f83d80bfe8
commit
3a2f900cfe
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@ -265,87 +265,72 @@ static void launch_dram(struct sysinfo *s)
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static void clkset0(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR16(0x400*ch + 0x5a0) = (MCHBAR16(0x400*ch + 0x5a0) & ~0xc440) |
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MCHBAR16_AND_OR(0x400*ch + 0x5a0, ~0xc440,
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(setting->clk_delay << 14) |
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(setting->db_sel << 6) |
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(setting->db_en << 10);
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MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0xf) |
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setting->tap;
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(setting->db_en << 10));
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MCHBAR8_AND_OR(0x400*ch + 0x581, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x581, ~0xf, setting->tap);
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}
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static void clkset1(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR32(0x400*ch + 0x5a0) = (MCHBAR32(0x400*ch + 0x5a0) & ~0x30880) |
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MCHBAR32_AND_OR(0x400*ch + 0x5a0, ~0x30880,
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(setting->clk_delay << 16) |
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(setting->db_sel << 7) |
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(setting->db_en << 11);
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MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0xf) |
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setting->tap;
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(setting->db_en << 11));
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MCHBAR8_AND_OR(0x400*ch + 0x582, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x582, ~0xf, setting->tap);
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}
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static void ctrlset0(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x3300000) |
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MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x3300000,
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(setting->clk_delay << 24) |
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(setting->db_sel << 20) |
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(setting->db_en << 21);
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MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0xf) |
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setting->tap;
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(setting->db_en << 21));
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MCHBAR8_AND_OR(0x400*ch + 0x584, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x584, ~0xf, setting->tap);
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}
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static void ctrlset1(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x18c00000) |
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MCHBAR32_AND_OR(0x400*ch + 0x59c, ~0x18c00000,
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(setting->clk_delay << 27) |
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(setting->db_sel << 22) |
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(setting->db_en << 23);
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MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0xf) |
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setting->tap;
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(setting->db_en << 23));
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MCHBAR8_AND_OR(0x400*ch + 0x585, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x585, ~0xf, setting->tap);
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}
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static void ctrlset2(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) |
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MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000,
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(setting->clk_delay << 14) |
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(setting->db_sel << 12) |
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(setting->db_en << 13);
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MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0xf) |
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setting->tap;
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(setting->db_en << 13));
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MCHBAR8_AND_OR(0x400*ch + 0x586, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x586, ~0xf, setting->tap);
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}
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static void ctrlset3(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) |
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MCHBAR32_AND_OR(0x400*ch + 0x598, ~0x18c00000,
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(setting->clk_delay << 10) |
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(setting->db_sel << 8) |
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(setting->db_en << 9);
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MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0xf) |
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setting->tap;
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(setting->db_en << 9));
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MCHBAR8_AND_OR(0x400*ch + 0x587, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x587, ~0xf, setting->tap);
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}
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static void cmdset(u8 ch, const struct dll_setting *setting)
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{
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MCHBAR8(0x400*ch + 0x598) = (MCHBAR8(0x400*ch + 0x598) & ~0x30) |
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(setting->clk_delay << 4);
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MCHBAR8(0x400*ch + 0x594) = (MCHBAR8(0x400*ch + 0x594) & ~0x60) |
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MCHBAR8_AND_OR(0x400*ch + 0x598, ~0x30, setting->clk_delay << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x594, ~0x60,
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(setting->db_sel << 5) |
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(setting->db_en << 6);
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MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0x70) |
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(setting->pi << 4);
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MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0xf) |
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setting->tap;
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(setting->db_en << 6));
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MCHBAR8_AND_OR(0x400*ch + 0x580, ~0x70, setting->pi << 4);
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MCHBAR8_AND_OR(0x400*ch + 0x580, ~0xf, setting->tap);
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}
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/**
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@ -356,52 +341,41 @@ void dqsset(u8 ch, u8 lane, const struct dll_setting *setting)
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{
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int rank;
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MCHBAR32(0x400 * ch + 0x5fc) = (MCHBAR32(0x400 * ch + 0x5fc)
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& ~(1 << (lane * 4 + 1)))
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| (setting->coarse << (lane * 4 + 1));
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MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4 + 1)),
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setting->coarse << (lane * 4 + 1));
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for (rank = 0; rank < 4; rank++) {
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MCHBAR32(0x400 * ch + 0x5b4 + rank * 4) =
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(MCHBAR32(0x400 * ch + 0x5b4 + rank * 4)
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& ~(0x201 << lane))
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| (setting->db_en << (9 + lane))
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| (setting->db_sel << lane);
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MCHBAR32_AND_OR(0x400 * ch + 0x5b4 + rank * 4, ~(0x201 << lane),
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(setting->db_en << (9 + lane)) |
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(setting->db_sel << lane));
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MCHBAR32(0x400*ch + 0x5c8 + rank * 4) =
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(MCHBAR32(0x400 * ch + 0x5c8 + rank * 4)
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& ~(0x3 << (16 + lane * 2)))
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| (setting->clk_delay << (16+lane * 2));
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MCHBAR32_AND_OR(0x400*ch + 0x5c8 + rank * 4,
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~(0x3 << (16 + lane * 2)),
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setting->clk_delay << (16+lane * 2));
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MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) =
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(MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0x7f)
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| (setting->pi << 4)
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| setting->tap;
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(MCHBAR8(0x400*ch + 0x520 + lane * 4) & ~0x7f) |
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(setting->pi << 4) |
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setting->tap;
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}
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}
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void dqset(u8 ch, u8 lane, const struct dll_setting *setting)
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{
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int rank;
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MCHBAR32(0x400 * ch + 0x5fc) = (MCHBAR32(0x400 * ch + 0x5fc)
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& ~(1 << (lane * 4)))
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| (setting->coarse << (lane * 4));
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MCHBAR32_AND_OR(0x400 * ch + 0x5fc, ~(1 << (lane * 4)),
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setting->coarse << (lane * 4));
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for (rank = 0; rank < 4; rank++) {
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MCHBAR32(0x400 * ch + 0x5a4 + rank * 4) =
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(MCHBAR32(0x400 * ch + 0x5a4 + rank * 4)
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& ~(0x201 << lane))
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| (setting->db_en << (9 + lane))
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| (setting->db_sel << lane);
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MCHBAR32_AND_OR(0x400 * ch + 0x5a4 + rank * 4, ~(0x201 << lane),
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(setting->db_en << (9 + lane)) |
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(setting->db_sel << lane));
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MCHBAR32(0x400 * ch + 0x5c8 + rank * 4) =
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(MCHBAR32(0x400 * ch + 0x5c8 + rank * 4)
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& ~(0x3 << (lane * 2)))
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| (setting->clk_delay << (2 * lane));
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MCHBAR32_AND_OR(0x400 * ch + 0x5c8 + rank * 4,
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~(0x3 << (lane * 2)), setting->clk_delay << (2 * lane));
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MCHBAR8(0x400*ch + 0x500 + lane * 4 + rank) =
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(MCHBAR8(0x400 * ch + 0x500 + lane * 4 + rank) & ~0x7f)
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| (setting->pi << 4)
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| setting->tap;
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MCHBAR8_AND_OR(0x400*ch + 0x500 + lane * 4 + rank, ~0x7f,
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(setting->pi << 4) | setting->tap);
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}
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}
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@ -545,10 +519,9 @@ static void program_timings(struct sysinfo *s)
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MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2);
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/* tWL - x ?? */
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MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4);
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MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) |
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adjusted_cas;
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MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) |
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((adjusted_cas + 9) << 8);
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MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf, adjusted_cas);
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MCHBAR16_AND_OR(0x400*i + 0x265, ~0x3f00,
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(adjusted_cas + 9) << 8);
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reg16 = (s->selected_timings.tRAS << 11) |
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((twl + 4 + s->selected_timings.tWR) << 6) |
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@ -583,11 +556,11 @@ static void program_timings(struct sysinfo *s)
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MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) |
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s->selected_timings.tRFC;
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MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe)
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| ((s->spd_type == DDR2 ? 100 : 256) << 1);
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MCHBAR16_AND_OR(0x400*i + 0x260, ~0x3fe,
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(s->spd_type == DDR2 ? 100 : 256) << 1);
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MCHBAR8(0x400*i + 0x264) = 0xff;
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MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) |
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s->selected_timings.tRAS;
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MCHBAR8_AND_OR(0x400*i + 0x25d, ~0x3f,
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s->selected_timings.tRAS);
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MCHBAR16(0x400*i + 0x244) = 0x2310;
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switch (s->selected_timings.mem_clk) {
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@ -599,8 +572,7 @@ static void program_timings(struct sysinfo *s)
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break;
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}
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MCHBAR8(0x400*i + 0x246) = (MCHBAR8(0x400*i + 0x246) & ~0x1f) |
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(reg8 << 2) | 1;
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MCHBAR8_AND_OR(0x400*i + 0x246, ~0x1f, (reg8 << 2) | 1);
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fsb = fsb2ps[s->selected_timings.fsb_clk];
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ddr = ddr2ps[s->selected_timings.mem_clk];
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@ -611,8 +583,7 @@ static void program_timings(struct sysinfo *s)
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ddr2mhz(s->selected_timings.mem_clk)) > 2) {
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reg32 |= 1 << 24;
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}
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MCHBAR32(0x400*i + 0x248) = (MCHBAR32(0x400*i + 0x248) & ~0x0f001f00) |
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reg32;
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MCHBAR32_AND_OR(0x400*i + 0x248, ~0x0f001f00, reg32);
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if (twl > 2)
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flag1 = 1;
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@ -778,8 +749,7 @@ static void program_dll(struct sysinfo *s)
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reg16 = 0;
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if ((s->spd_type == DDR3) && (i == 0))
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reg16 = (0x3 << 12);
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MCHBAR16(0x400*i + 0x59c) = (MCHBAR16(0x400*i + 0x59c)
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& ~0x3000) | reg16;
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MCHBAR16_AND_OR(0x400*i + 0x59c, ~0x3000, reg16);
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reg32 = 0;
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FOR_EACH_RANK_IN_CHANNEL(r) {
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@ -818,9 +788,8 @@ static void program_dll(struct sysinfo *s)
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} else { /* DDR3 */
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FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
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MCHBAR8(0x400 * i + 0x5a0 + 3) =
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MCHBAR8(0x400 * i + 0x5a0 + 3)
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& ~rank2clken[r + i * 4];
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MCHBAR8_AND(0x400 * i + 0x5a0 + 3,
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~rank2clken[r + i * 4]);
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}
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}
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@ -1142,58 +1111,46 @@ static void prog_rcomp(struct sysinfo *s)
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FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
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for (j = 0; j < 6; j++) {
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if (j == 0) {
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MCHBAR32(0x400*i + addr[j]) =
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(MCHBAR32(0x400*i + addr[j]) & ~0xff000)
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| 0xaa000;
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MCHBAR32_AND_OR(0x400*i + addr[j], ~0xff000,
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0xaa000);
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MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,
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0x6666);
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for (k = 0; k < 8; k++) {
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MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) =
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(MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2))
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& ~0x3f3f3f3f) | x32a[k];
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MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) =
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(MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2))
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& ~0x3f3f3f3f) | x32a[k];
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MCHBAR32_AND_OR(0x400*i + addr[j] +
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0xe + (k << 2),
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~0x3f3f3f3f, x32a[k]);
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MCHBAR32_AND_OR(0x400*i + addr[j] +
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0x2e + (k << 2),
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~0x3f3f3f3f, x32a[k]);
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}
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} else {
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MCHBAR16(0x400*i + addr[j]) =
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(MCHBAR16(0x400*i + addr[j])
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& ~0xf000) | 0xa000;
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MCHBAR16(0x400*i + addr[j] + 4) =
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(MCHBAR16(0x400*i + addr[j] + 4)
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& ~0xffff) | x378[j];
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MCHBAR32(0x400*i + addr[j] + 0xe) =
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(MCHBAR32(0x400*i + addr[j] + 0xe)
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& ~0x3f3f3f3f) | x382[j];
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MCHBAR32(0x400*i + addr[j] + 0x12) =
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(MCHBAR32(0x400*i + addr[j] + 0x12)
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& ~0x3f3f3f3f) | x386[j];
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MCHBAR32(0x400*i + addr[j] + 0x16) =
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(MCHBAR32(0x400*i + addr[j] + 0x16)
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& ~0x3f3f3f3f) | x38a[j];
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MCHBAR32(0x400*i + addr[j] + 0x1a) =
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(MCHBAR32(0x400*i + addr[j] + 0x1a)
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& ~0x3f3f3f3f) | x38e[j];
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MCHBAR32(0x400*i + addr[j] + 0x1e) =
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(MCHBAR32(0x400*i + addr[j] + 0x1e)
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& ~0x3f3f3f3f) | x392[j];
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MCHBAR32(0x400*i + addr[j] + 0x22) =
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(MCHBAR32(0x400*i + addr[j] + 0x22)
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& ~0x3f3f3f3f) | x396[j];
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MCHBAR32(0x400*i + addr[j] + 0x26) =
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(MCHBAR32(0x400*i + addr[j] + 0x26)
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& ~0x3f3f3f3f) | x39a[j];
|
||||
MCHBAR32(0x400*i + addr[j] + 0x2a) =
|
||||
(MCHBAR32(0x400*i + addr[j] + 0x2a)
|
||||
& ~0x3f3f3f3f) | x39e[j];
|
||||
MCHBAR16_AND_OR(0x400*i + addr[j],
|
||||
~0xf000, 0xa000);
|
||||
MCHBAR16_AND_OR(0x400*i + addr[j] + 4,
|
||||
~0xffff, x378[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0xe,
|
||||
~0x3f3f3f3f, x382[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x12,
|
||||
~0x3f3f3f3f, x386[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x16,
|
||||
~0x3f3f3f3f, x38a[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1a,
|
||||
~0x3f3f3f3f, x38e[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x1e,
|
||||
~0x3f3f3f3f, x392[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x22,
|
||||
~0x3f3f3f3f, x396[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x26,
|
||||
~0x3f3f3f3f, x39a[j]);
|
||||
MCHBAR32_AND_OR(0x400*i + addr[j] + 0x2a,
|
||||
~0x3f3f3f3f, x39e[j]);
|
||||
}
|
||||
if (s->spd_type == DDR3
|
||||
&& BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
|
||||
MCHBAR16(0x378 + 0x400 * i) =
|
||||
(MCHBAR16(0x378 + 0x400 * i)
|
||||
& ~0xffff) | 0xcccc;
|
||||
if (s->spd_type == DDR3 &&
|
||||
BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) {
|
||||
MCHBAR16_AND_OR(0x378 + 0x400 * i,
|
||||
~0xffff, 0xcccc);
|
||||
}
|
||||
MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j];
|
||||
MCHBAR8_AND_OR(0x400*i + addr[j], ~1, bit[j]);
|
||||
}
|
||||
reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36;
|
||||
MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8);
|
||||
|
|
@ -1272,8 +1229,7 @@ static void program_odt(struct sysinfo *s)
|
|||
reg16 &= ~0xfff;
|
||||
reg16 |= (s->spd_type == DDR2 ? 0x66b : 0x778);
|
||||
MCHBAR16(0x400*i + 0x29c) = reg16;
|
||||
MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260)
|
||||
& ~0x70e3c00) | 0x3063c00;
|
||||
MCHBAR32_AND_OR(0x400*i + 0x260, ~0x70e3c00, 0x3063c00);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1843,9 +1799,8 @@ static void set_enhanced_mode(struct sysinfo *s)
|
|||
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0);
|
||||
pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1);
|
||||
MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2
|
||||
| (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz
|
||||
? 0x20000 : 0);
|
||||
MCHBAR32_AND_OR(0xfa0, ~0x20002, 0x2 | (s->selected_timings.fsb_clk ==
|
||||
FSB_CLOCK_1333MHz ? 0x20000 : 0));
|
||||
reg32 = 0x219100c2;
|
||||
if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz) {
|
||||
reg32 |= 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue