GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/intel/car/core2: Improve a few things 

This changes the following:
- compute amount variable MTRR's during runtime
- Wait for all CPU's to be in Wait for SIPI state after sending init
  INIT IPI to all AP's
- compute the PHYSMASK high during runtime and preload it to the
  MTRR_PHYS_MASK msr's

Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans 2018-06-03 11:02:54 +02:00
parent 7a8205ba35
commit 3aa9adba67
1 changed files with 67 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

95
src/cpu/intel/car/core2/cache_as_ram.S
View File

@ -3,6 +3,7 @@
* *
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -18,8 +19,6 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
@ -37,18 +36,40 @@ cache_as_ram:
movl $0xFEE00300, %esi movl $0xFEE00300, %esi
movl %eax, (%esi) movl %eax, (%esi)
/* Zero out all fixed range and variable range MTRRs. */ /* All CPUs need to be in Wait for SIPI state */
movl $mtrr_table, %esi wait_for_sipi:
movl $((mtrr_table_end - mtrr_table) >> 1), %edi movl (%esi), %eax
xorl %eax, %eax bt $12, %eax
xorl %edx, %edx jc wait_for_sipi
clear_mtrrs:
movw (%esi), %bx post_code(0x22)
movzx %bx, %ecx
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list_size, %ebx
xor %eax, %eax
xor %edx, %edx
clear_fixed_mtrr:
add $-2, %ebx
movzwl fixed_mtrr_list(%ebx), %ecx
wrmsr wrmsr
add $2, %esi jnz clear_fixed_mtrr
dec %edi
jnz clear_mtrrs /* Figure put how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx
rdmsr
movzb %al, %ebx /* Number of variable MTRRs */
mov $MTRR_PHYS_BASE(0), %ecx
xor %eax, %eax
xor %edx, %edx
clear_var_mtrr:
wrmsr
inc %ecx
wrmsr
inc %ecx
dec %ebx
jnz clear_var_mtrr
post_code(0x22) post_code(0x22)
/* Configure the default memory type to uncacheable. */ /* Configure the default memory type to uncacheable. */
@ -57,6 +78,24 @@ clear_mtrrs:
andl $(~0x00000cff), %eax andl $(~0x00000cff), %eax
wrmsr wrmsr
/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */
movl $0x80000008, %eax
cpuid
movb %al, %cl
sub $32, %cl
movl $1, %edx
shl %cl, %edx
subl $1, %edx
/* Preload high word of address mask (in %edx) for Variable
MTRRs 0 and 1. */
addrsize_set_high:
xorl %eax, %eax
movl $MTRR_PHYS_MASK(0), %ecx
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
wrmsr
post_code(0x23) post_code(0x23)
/* Set Cache-as-RAM base address. */ /* Set Cache-as-RAM base address. */
movl $(MTRR_PHYS_BASE(0)), %ecx movl $(MTRR_PHYS_BASE(0)), %ecx
@ -67,8 +106,8 @@ clear_mtrrs:
post_code(0x24) post_code(0x24)
/* Set Cache-as-RAM mask. */ /* Set Cache-as-RAM mask. */
movl $(MTRR_PHYS_MASK(0)), %ecx movl $(MTRR_PHYS_MASK(0)), %ecx
rdmsr
movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
wrmsr wrmsr
post_code(0x25) post_code(0x25)
@ -95,7 +134,6 @@ clear_mtrrs:
movl $CACHE_AS_RAM_BASE, %esi movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
// movl $0x23322332, %eax
xorl %eax, %eax xorl %eax, %eax
rep stosl rep stosl
@ -118,7 +156,7 @@ clear_mtrrs:
wrmsr wrmsr
movl $MTRR_PHYS_MASK(1), %ecx movl $MTRR_PHYS_MASK(1), %ecx
movl $CPU_PHYSMASK_HI, %edx rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr wrmsr
@ -149,17 +187,18 @@ before_romstage:
hlt hlt
jmp .Lhlt jmp .Lhlt
mtrr_table: fixed_mtrr_list:
/* Fixed MTRRs */ .word MTRR_FIX_64K_00000
.word 0x250, 0x258, 0x259 .word MTRR_FIX_16K_80000
.word 0x268, 0x269, 0x26A .word MTRR_FIX_16K_A0000
.word 0x26B, 0x26C, 0x26D .word MTRR_FIX_4K_C0000
.word 0x26E, 0x26F .word MTRR_FIX_4K_C8000
/* Variable MTRRs */ .word MTRR_FIX_4K_D0000
.word 0x200, 0x201, 0x202, 0x203 .word MTRR_FIX_4K_D8000
.word 0x204, 0x205, 0x206, 0x207 .word MTRR_FIX_4K_E0000
.word 0x208, 0x209, 0x20A, 0x20B .word MTRR_FIX_4K_E8000
.word 0x20C, 0x20D, 0x20E, 0x20F .word MTRR_FIX_4K_F0000
mtrr_table_end: .word MTRR_FIX_4K_F8000
fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: _cache_as_ram_setup_end: