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nb/intel/sandybridge: Use the new IOSAV struct API 

Now that we have created the IOSAV API, we can put it to good use.
Drop all the helper macros and replace them with struct constructs.

Tested with BUILD_TIMELESS=1, ASUS P8Z77-V LX2 remains unchanged.

Change-Id: Ib366e364df11c9bb240cdfbce418540ec715c634
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-05-03 00:25:02 +02:00
parent 38d901e88d
commit 3abd206d4f
3 changed files with 1740 additions and 463 deletions
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58
src/northbridge/intel/sandybridge/mchbar_regs.h
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@ -188,64 +188,6 @@
* [6] Cleared with a new sequence, and set when done and refresh counter is drained.
*/
/* Temporary IOSAV register macros to verifiably split bitfields */
#define SUBSEQ_CTRL(reps, gap, post, dir) (((reps) << 0) | \
((gap) << 10) | \
((post) << 16) | \
((dir) << 26))
#define SSQ_NA 0 /* Non-data */
#define SSQ_RD 1 /* Read */
#define SSQ_WR 2 /* Write */
#define SSQ_RW 3 /* Read and write */
#define SP_CMD_ADDR(addr, rowbits, bank, rank) (((addr) << 0) | \
((rowbits) << 16) | \
((bank) << 20) | \
((rank) << 24))
#define ADDR_UPDATE(addr_1, addr_8, bank, rank, wrap, lfsr, rate, xors) (((addr_1) << 0) | \
((addr_8) << 1) | \
((bank) << 2) | \
((rank) << 3) | \
((wrap) << 5) | \
((lfsr) << 10) | \
((rate) << 12) | \
((xors) << 16))
#define IOSAV_SUBSEQUENCE(ch, n, cmd, ranksel, reps, gap, post, dir, addr, row_bits, bank_addr, rank_addr, addr_1, addr_8, upd_bank, upd_rank, wrap, lfsr, rate, xors) \
do { \
const struct iosav_ssq ssq = { \
.sp_cmd_ctrl = { \
.command = cmd, \
.ranksel_ap = ranksel, \
}, \
.subseq_ctrl = { \
.cmd_executions = reps, \
.cmd_delay_gap = gap, \
.post_ssq_wait = post, \
.data_direction = dir, \
}, \
.sp_cmd_addr = { \
.address = addr, \
.rowbits = row_bits, \
.bank = bank_addr, \
.rank = rank_addr, \
}, \
.addr_update = { \
.inc_addr_1 = addr_1, \
.inc_addr_8 = addr_8, \
.inc_bank = upd_bank, \
.inc_rank = upd_rank, \
.addr_wrap = wrap, \
.lfsr_upd = lfsr, \
.upd_rate = rate, \
.lfsr_xors = xors, \
}, \
}; \
iosav_write_ssq(ch, &ssq); \
} while (0)
/* Indexed register helper macros */
#define Gz(r, z) ((r) + ((z) << 8))
#define Ly(r, y) ((r) + ((y) << 2))

2138
src/northbridge/intel/sandybridge/raminit_common.c
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File diff suppressed because it is too large Load Diff

7
src/northbridge/intel/sandybridge/raminit_common.h
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@ -25,6 +25,7 @@
#define NUM_SLOTS 2
#define NUM_LANES 9
/* IOSAV_n_SP_CMD_CTRL DRAM commands */
#define IOSAV_MRS (0xf000)
#define IOSAV_PRE (0xf002)
#define IOSAV_ZQCS (0xf003)
@ -34,6 +35,12 @@
#define IOSAV_WR (0xf201)
#define IOSAV_NOP (0xf207)
/* IOSAV_n_SUBSEQ_CTRL data direction */
#define SSQ_NA 0 /* Non-data */
#define SSQ_RD 1 /* Read */
#define SSQ_WR 2 /* Write */
#define SSQ_RW 3 /* Read and write */
struct iosav_ssq {
/* IOSAV_n_SP_CMD_CTRL */
union {