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soc/intel/skylake: Correct Cache as ram size 

DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to
set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000
is used to calculate the _car_region_end in car.ld. If the FSP CAR
requirement is greater than or even close to DCACHE_RAM_SIZE then,
the CAR region for FSP will be determined to be below the overall
CAR region boundary i.e, out of CAR memory range.

This is working with FSP 1.1 because we provide the FspCarSize
and FspCarBase explicitly in a UPD. Hence, FSP is still able to
use the upper region of CAR memory for its purpose.
However, it will be a problem in case of FSP2.0 where FSP usable CAR
is calculated using _car_region_end.

So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set
DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB)

Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16236
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Rizwan Qureshi 2016-08-14 15:48:33 +05:30 committed by Martin Roth
parent ecd9a94213
commit 3ad63565a5
3 changed files with 4 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/skylake/Kconfig
View File

@ -84,7 +84,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM" hex "Length in bytes of cache-as-RAM"
default 0x10000 default 0x40000
help help
The size of the cache-as-ram region required during bootblock The size of the cache-as-ram region required during bootblock
and/or romstage. and/or romstage.
@ -199,10 +199,6 @@ config NHLT_SSM4567
help help
Include DSP firmware settings for ssm4567 smart amplifier. Include DSP firmware settings for ssm4567 smart amplifier.
config DCACHE_RAM_SIZE_TOTAL
hex
default 0x40000
config SKIP_FSP_CAR config SKIP_FSP_CAR
bool "Skip cache as RAM setup in FSP" bool "Skip cache as RAM setup in FSP"
default y default y

4
src/soc/intel/skylake/bootblock/cache_as_ram.S
View File

@ -116,7 +116,7 @@ clear_var_mtrr:
/* Configure the MTRR mask for the size region */ /* Configure the MTRR mask for the size region */
mov $MTRR_PHYS_MASK(0), %ecx mov $MTRR_PHYS_MASK(0), %ecx
mov $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax /* size mask */ mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */
dec %eax dec %eax
not %eax not %eax
or $MTRR_PHYS_MASK_VALID, %eax or $MTRR_PHYS_MASK_VALID, %eax
@ -216,7 +216,7 @@ find_llc_subleaf:
wrmsr wrmsr
movl $CONFIG_DCACHE_RAM_BASE, %edi movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx shr $0x02, %ecx
movl $CACHE_INIT_VALUE, %eax movl $CACHE_INIT_VALUE, %eax
cld cld

2
src/soc/intel/skylake/romstage/romstage.c
View File

@ -93,7 +93,7 @@ void soc_memory_init_params(struct romstage_params *params,
upd->DdrFreqLimit = config->DdrFreqLimit; upd->DdrFreqLimit = config->DdrFreqLimit;
if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) {
upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; upd->FspCarBase = CONFIG_DCACHE_RAM_BASE;
upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE;
} }
} }