mainboard/intel: Add Stargo2
The Intel Stargo2 is a communications device reference design. This mainboard uses the Sandy/Ivy Bridge and is paired with the i89xx southbridge. The FSP package is available from Intel: https://intel.com/fsp. Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones
Martin Roth
parent
2d72345f80
commit
3b0a626edc
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if BOARD_INTEL_STARGO2
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select CPU_INTEL_SOCKET_BGA1284
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select NORTHBRIDGE_INTEL_FSP_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_FSP_I89XX
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select BOARD_ROMSIZE_KB_4096
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select MMCONF_SUPPORT
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select SUPERIO_WINBOND_WPCD376I
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select SUPERIO_INTEL_I8900
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select SERIRQ_CONTINUOUS_MODE
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select ENABLE_VMX
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config MAINBOARD_DIR
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string
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default intel/stargo2
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config MAINBOARD_PART_NUMBER
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string
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default "Stargo2"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf8000000
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAX_CPUS
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int
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default 16
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config VGA_BIOS
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bool
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default n
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endif # BOARD_INTEL_STARGO2
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@ -0,0 +1,2 @@
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config BOARD_INTEL_STARGO2
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bool "Stargo2"
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/*
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* ec.asl
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*
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* This file is included by lpc.asl in the southbridge directory.
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* It is intended to be used to include any embedded controller
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* specific ASL.
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*/
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@ -0,0 +1,99 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* This is board specific information: IRQ routing for Sandybridge */
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// PCI Interrupt Routing
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Method(_PRT)
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{
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If (PICM) {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, 0, 16 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, 0, 19 },
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// Network 0:19.0
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Package() { 0x0019ffff, 0, 0, 20 },
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, 0, 21 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, 0, 22 },
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/* MEI */
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Package() { 0x0016ffff, 0, 0, 16 },
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Package() { 0x0016ffff, 1, 0, 17 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, 0, 16 },
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Package() { 0x001cffff, 1, 0, 17 },
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Package() { 0x001cffff, 2, 0, 18 },
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Package() { 0x001cffff, 3, 0, 19 },
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// EHCI #1 0:1d.0
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Package() { 0x001dffff, 0, 0, 23 },
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// LPC devices 0:1f.0
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Package() { 0x001fffff, 0, 0, 16 },
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Package() { 0x001fffff, 1, 0, 19 },
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Package() { 0x001fffff, 2, 0, 18 },
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Package() { 0x001fffff, 3, 0, 16 },
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})
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} Else {
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Return (Package() {
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// Onboard graphics (IGD) 0:2.0
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Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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// XHCI 0:14.0
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Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI #2 0:19.0
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Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
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// EHCI #2 0:1a.0
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Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
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// High Definition Audio 0:1b.0
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Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
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/* Management Engine Interface */
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Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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// PCIe Root Ports 0:1c.x
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Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
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Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
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// EHCI #1 0:1d.0
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Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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// LPC device 0:1f.0
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Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
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Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
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Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
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Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
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})
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}
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* Power Button */
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Device (PWRB)
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{
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Name(_HID, EisaId("PNP0C0C"))
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// Wake
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Name(_PRW, Package(){0x1d, 0x05})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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/* NVS has a flag to determine USB policy in S3 */
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if (S3U0) {
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Store (One, GP47) // Enable USB0
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} Else {
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Store (Zero, GP47) // Disable USB0
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}
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/* NVS has a flag to determine USB policy in S3 */
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if (S3U1) {
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Store (One, GP56) // Enable USB1
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} Else {
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Store (Zero, GP56) // Disable USB1
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}
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc.
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*/
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/* Values should match those defined in devicetree.cb */
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/msr.h>
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#include <southbridge/intel/fsp_i89xx/pch.h>
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#include <southbridge/intel/fsp_i89xx/nvs.h>
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#include "thermal.h"
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static global_nvs_t *gnvs_;
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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}
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs_ = gnvs;
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->pcnt = dev_count_cpu();
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/* Enable USB ports in S3 */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/*
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* Enable USB ports in S5 by default
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* to be consistent with back port behavior
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*/
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gnvs->s5u0 = 1;
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gnvs->s5u1 = 1;
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acpi_update_thermal_table(gnvs);
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}
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unsigned long acpi_fill_madt(unsigned long current)
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{
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/* Local APICs */
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current = acpi_create_madt_lapics(current);
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/* IOAPIC */
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
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2, IO_APIC_ADDR, 0);
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/* INT_SRC_OVR */
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 0, 2, 0);
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
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current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
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return current;
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}
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Category: eval
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Release year: 2010
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
|
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## it under the terms of the GNU General Public License as published by
|
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## the Free Software Foundation; version 2 of the License.
|
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##
|
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## This program is distributed in the hope that it will be useful,
|
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc.
|
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##
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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388 4 r 0 reboot_bits
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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#411 5 r 0 unused
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# coreboot config options: bootloader
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#Used by ChromeOS:
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416 128 r 0 vbnv
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#544 440 r 0 unused
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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|
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# coreboot config options: check sums
|
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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# -----------------------------------------------------------------
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||||
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enumerations
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|
||||
#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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||||
5 1 57600
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||||
5 2 38400
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||||
5 3 19200
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||||
5 4 9600
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||||
5 5 4800
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||||
5 6 2400
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5 7 1200
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||||
6 1 Emergency
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||||
6 2 Alert
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||||
6 3 Critical
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||||
6 4 Error
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||||
6 5 Warning
|
||||
6 6 Notice
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||||
6 7 Info
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||||
6 8 Debug
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||||
6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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||||
8 0 AHCI
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8 1 Compatible
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# -----------------------------------------------------------------
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checksums
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||||
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checksum 392 415 984
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@ -0,0 +1,97 @@
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chip northbridge/intel/fsp_sandybridge
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device cpu_cluster 0 on
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chip cpu/intel/socket_BGA1284
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device lapic 0 on end
|
||||
end
|
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chip cpu/intel/fsp_model_206ax
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# Magic APIC ID to locate this chip
|
||||
device lapic 0xACAC off end
|
||||
|
||||
register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3)
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register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
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||||
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
|
||||
|
||||
register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3)
|
||||
register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
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||||
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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end
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||||
end
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||||
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||||
device domain 0 on
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||||
device pci 00.0 on end # host bridge
|
||||
device pci 01.0 on end # host bridge (slot 2 - black x16 slot (only x8))
|
||||
device pci 01.1 on end # host bridge (PCIe Ethernet controllers)
|
||||
device pci 01.2 off end # host bridge (off - no additional bifurcation)
|
||||
device pci 02.0 off end # vga controller
|
||||
device pci 06.0 on end # host bridge (slot 1 - blue x4 slot)
|
||||
|
||||
chip southbridge/intel/fsp_i89xx # Intel Series 89xx Cave Creek PCH
|
||||
register "ide_legacy_combined" = "0x0"
|
||||
register "sata_ahci" = "0x01"
|
||||
register "sata_port_map" = "0x30"
|
||||
register "c2_latency" = "1"
|
||||
register "p_cnt_throttling_supported" = "0"
|
||||
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 1c.0 on end # PCIe Port #1 (Slot #3 - x1)
|
||||
device pci 1c.1 on end # PCIe Port #2 (Slot #4 - x1)
|
||||
device pci 1c.2 on end # PCIe Port #3 (Slot #5 - x1)
|
||||
device pci 1c.3 on end # PCIe Port #4 (Slot #6 - x1)
|
||||
device pci 1d.0 on end # USB2 EHCI #1
|
||||
device pci 1f.0 on # LPC bridge
|
||||
|
||||
# The top serial port is controlled by jumper
|
||||
# J3a3. If the jumper is off, the serial
|
||||
# port connector is routed to the SIO. If
|
||||
# the jumper is on, the connector goes to
|
||||
# the PCH's serial port. There is no way
|
||||
# to tell in software which it's connected
|
||||
# to.
|
||||
|
||||
chip superio/intel/i8900
|
||||
device pnp 4e.4 on # Com3
|
||||
io 0x60 = 0x3E8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 4e.5 on # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 4e.6 on # Watchdog Timer
|
||||
io 0x60 = 0x600
|
||||
irq 0x70 = 7
|
||||
end
|
||||
end
|
||||
|
||||
chip superio/winbond/wpcd376i
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 off end # LPT
|
||||
device pnp 2e.2 off end # IR
|
||||
device pnp 2e.3 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 off end # System wakeup
|
||||
device pnp 2e.5 on # PS/2 mouse
|
||||
irq 0x70 = 0x0C
|
||||
end
|
||||
device pnp 2e.6 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 0x01
|
||||
end
|
||||
device pnp 2e.7 off end # GPIO
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on end # SATA Controller 1
|
||||
device pci 1f.3 on end # SMBus
|
||||
device pci 1f.5 off end # SATA Controller 2
|
||||
device pci 1f.6 on end # Thermal
|
||||
device pci 1f.7 on end # WDT
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <southbridge/intel/fsp_i89xx/acpi/platform.asl>
|
||||
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/fsp_i89xx/acpi/globalnvs.asl>
|
||||
|
||||
// General Purpose Events
|
||||
//#include "acpi/gpe.asl"
|
||||
|
||||
#include <cpu/intel/fsp_model_206ax/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl>
|
||||
#include <southbridge/intel/fsp_i89xx/acpi/pch.asl>
|
||||
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/fsp_i89xx/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_GPIO_H
|
||||
#define MAINBOARD_GPIO_H
|
||||
|
||||
#include "southbridge/intel/fsp_i89xx/gpio.h"
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
|
||||
/* 1. The following bits are always 1 because they are always
|
||||
* unMultiplexed: 0, 8, 15, 24, 27, and 28.
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPIO 17
|
||||
* This strap along with the fuse setting determines DMI TX
|
||||
* voltage level and TX/RX termination.
|
||||
* PU - SNB GLD (J1G7 Open)
|
||||
* PD - IVB GLD (J1G7 Jumpered)
|
||||
*
|
||||
* GPIO 25 - Output
|
||||
* Low = 1.35V DDR3
|
||||
* High = 1.5V DDR3
|
||||
*
|
||||
* 1.35V DDR3 is Forced by J9C2 Jumpered
|
||||
* 1.35V / 1.5V switching by GPIO 25 if J9C2 is open
|
||||
*
|
||||
* GPIO 30 - Core OSC power strap
|
||||
* Low SFR OUT (INT) J1J1 Jumpered (Default)
|
||||
* High VCCP1P0_STBY (EXT) J1J1 Open
|
||||
*/
|
||||
|
||||
.gpio0 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio1 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio2 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio3 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio4 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio5 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO3 - MLR TODO: What does this do? */
|
||||
.gpio6 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO4 - MLR TODO: What does this do? */
|
||||
.gpio7 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio8 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio9 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio10 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio11 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio12 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio13 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio14 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio15 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO0_SUS - MLR TODO*/
|
||||
.gpio16 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio17 = GPIO_MODE_GPIO, /* PCH_TACH0_GP17 Note:- TODO: What register does this?*/
|
||||
.gpio18 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio19 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio20 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio21 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio22 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio23 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio24 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio25 = GPIO_MODE_GPIO, /* VDD1P5_DDR OUTPUT LEVEL - MLR TODO: Config for this? Detect memory? */
|
||||
.gpio26 = GPIO_MODE_GPIO, /* SIO_PME_N - MLR TODO: Configure this */
|
||||
.gpio27 = GPIO_MODE_GPIO, /* FP_LED_YLW_N - MLR TODO: Configure this */
|
||||
.gpio28 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio29 = GPIO_MODE_NONE, /* NA */
|
||||
.gpio30 = GPIO_MODE_GPIO, /* PCH_SUS_PWR_ACK_GP30 - MLR TODO */
|
||||
.gpio31 = GPIO_MODE_NONE, /* Unused */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio1 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio2 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio3 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio4 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio5 = GPIO_DIR_OUTPUT, /* GPIO */
|
||||
.gpio6 = GPIO_DIR_OUTPUT, /* GPIO */
|
||||
.gpio7 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio8 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio9 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio10 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio11 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio12 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio13 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio14 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio15 = GPIO_DIR_OUTPUT, /* GPIO */
|
||||
.gpio16 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio17 = GPIO_DIR_INPUT, /* GPIO */
|
||||
.gpio18 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio19 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio20 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio21 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio22 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio23 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio24 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio25 = GPIO_DIR_OUTPUT, /* GPIO */
|
||||
.gpio26 = GPIO_DIR_INPUT, /* GPIO */
|
||||
.gpio27 = GPIO_DIR_OUTPUT, /* GPIO */
|
||||
.gpio28 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio29 = GPIO_DIR_INPUT, /* NA */
|
||||
.gpio30 = GPIO_DIR_OUTPUT, /* GPIO */
|
||||
.gpio31 = GPIO_DIR_INPUT, /* Unused */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio0 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio1 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio2 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio3 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio4 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio5 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio6 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio7 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio8 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio9 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio10 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio11 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio12 = GPIO_LEVEL_LOW, /* Unused */
|
||||
.gpio13 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio14 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio15 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio16 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio17 = GPIO_LEVEL_HIGH, /* GPIO In */
|
||||
.gpio18 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio19 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio20 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio21 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio22 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio23 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio24 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio25 = GPIO_LEVEL_HIGH, /* GPIO Out */
|
||||
.gpio26 = GPIO_LEVEL_HIGH, /* GPIO In */
|
||||
.gpio27 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio28 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio29 = GPIO_LEVEL_HIGH, /* NA */
|
||||
.gpio30 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio31 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
/*
|
||||
* Gpio 46: Bios Recovery strap
|
||||
* High = Normal mode - J5A3 (Open)
|
||||
* Low = Recovery Mode - J5A3 (Jumpered)
|
||||
*/
|
||||
.gpio32 = GPIO_MODE_GPIO, /* PCH_CLKRUN_N - MLR TODO:*/
|
||||
.gpio33 = GPIO_MODE_NONE, /* Unused (SECURITY OVERRIDE STRAP (J1G4)) */
|
||||
.gpio34 = GPIO_MODE_NONE, /* Unused*/
|
||||
.gpio35 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO2 : MLR TODO*/
|
||||
.gpio36 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio37 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio38 = GPIO_MODE_GPIO, /* Dev Kit Board Version high bit */
|
||||
.gpio39 = GPIO_MODE_GPIO, /* Dev Kit Board Version low bit */
|
||||
.gpio40 = GPIO_MODE_NATIVE, /* PCH_GP40_OC_N<1> */
|
||||
.gpio41 = GPIO_MODE_NATIVE, /* PCH_GP41_OC_N<2> */
|
||||
.gpio42 = GPIO_MODE_NATIVE, /* PCH_GP42_OC_N<3> */
|
||||
.gpio43 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio44 = GPIO_MODE_GPIO, /* CONN_GBE_GPIO1_SUS : MLR TODO */
|
||||
.gpio45 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio46 = GPIO_MODE_GPIO, /* BIOS RECOVERY STRAP - Note : MLR TODO */
|
||||
.gpio47 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio48 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio49 = GPIO_MODE_NONE, /* Unused (TEMP_ALERT# J2H2 test jumper) */
|
||||
.gpio50 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio51 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio52 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio53 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio54 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio55 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio56 = GPIO_MODE_GPIO, /* CONN_GBE_RESET_N */
|
||||
.gpio57 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio58 = GPIO_MODE_NATIVE, /* PCH_SML1_CLK */
|
||||
.gpio59 = GPIO_MODE_NATIVE, /* PCH_GP59_OC_N<0> */
|
||||
.gpio60 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio61 = GPIO_MODE_NATIVE, /* PCH_SUS_STAT_N */
|
||||
.gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK */
|
||||
.gpio63 = GPIO_MODE_NATIVE, /* PCH_SLP_S5_N */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT, /* GPIO Out */
|
||||
.gpio33 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio34 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio35 = GPIO_DIR_OUTPUT, /* GPIO Out */
|
||||
.gpio36 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio37 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio38 = GPIO_DIR_INPUT, /* GPIO In */
|
||||
.gpio39 = GPIO_DIR_INPUT, /* GPIO In */
|
||||
.gpio40 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio41 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio42 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio43 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio44 = GPIO_DIR_OUTPUT, /* GPIO Out */
|
||||
.gpio45 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio46 = GPIO_DIR_INPUT, /* GPIO In */
|
||||
.gpio47 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio48 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio49 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio50 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio51 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio52 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio53 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio54 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio55 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio56 = GPIO_DIR_OUTPUT, /* GPIO Out */
|
||||
.gpio57 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio58 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio59 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio60 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio61 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio62 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio63 = GPIO_DIR_INPUT, /* Native */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH, /* GPIO Out */
|
||||
.gpio33 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio34 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio35 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio36 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio37 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio38 = GPIO_LEVEL_HIGH, /* GPIO In */
|
||||
.gpio39 = GPIO_LEVEL_HIGH, /* GPIO In */
|
||||
.gpio40 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio41 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio42 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio43 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio44 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio45 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio46 = GPIO_LEVEL_HIGH, /* GPIO In */
|
||||
.gpio47 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio48 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio49 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio50 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio51 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio52 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio53 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio54 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio55 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio56 = GPIO_LEVEL_LOW, /* GPIO Out */
|
||||
.gpio57 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio58 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio59 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio60 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio61 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio62 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio63 = GPIO_LEVEL_HIGH, /* Native */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio72 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio73 = GPIO_MODE_NONE, /* Unused */
|
||||
.gpio74 = GPIO_MODE_NATIVE, /* PCH_SML1ALERT */
|
||||
.gpio75 = GPIO_MODE_NATIVE, /* PCH_SML1_DAT */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio72 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio73 = GPIO_DIR_INPUT, /* Unused */
|
||||
.gpio74 = GPIO_DIR_INPUT, /* Native */
|
||||
.gpio75 = GPIO_DIR_INPUT, /* Native */
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio72 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio73 = GPIO_LEVEL_HIGH, /* Unused */
|
||||
.gpio74 = GPIO_LEVEL_HIGH, /* Native */
|
||||
.gpio75 = GPIO_LEVEL_HIGH, /* Native */
|
||||
};
|
||||
|
||||
const struct pch_gpio_map gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <device/device.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
#include <southbridge/intel/fsp_i89xx/pch.h>
|
||||
|
||||
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
// mainboard_enable is executed as first thing after
|
||||
// enumerate_buses().
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2013 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <southbridge/intel/fsp_i89xx/nvs.h>
|
||||
#include <southbridge/intel/fsp_i89xx/pch.h>
|
||||
#include <southbridge/intel/fsp_i89xx/me.h>
|
||||
#include <northbridge/intel/fsp_sandybridge/sandybridge.h>
|
||||
#include <cpu/intel/fsp_model_206ax/model_206ax.h>
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
u8 reg8;
|
||||
|
||||
switch (slp_typ) {
|
||||
case SLP_TYP_S3:
|
||||
case SLP_TYP_S4:
|
||||
case SLP_TYP_S5:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static int mainboard_finalized = 0;
|
||||
|
||||
int mainboard_smi_apmc(u8 apmc)
|
||||
{
|
||||
switch (apmc) {
|
||||
case APM_CNT_FINALIZE:
|
||||
if (mainboard_finalized) {
|
||||
printk(BIOS_DEBUG, "SMI#: Already finalized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
intel_me_finalize_smm();
|
||||
intel_pch_finalize_smm();
|
||||
intel_sandybridge_finalize_smm();
|
||||
intel_model_206ax_finalize_smm();
|
||||
|
||||
mainboard_finalized = 1;
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <lib.h>
|
||||
#include <timestamp.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <cbmem.h>
|
||||
#include <console/console.h>
|
||||
#include <halt.h>
|
||||
#include <reset.h>
|
||||
#include <fsp_util.h>
|
||||
#include <northbridge/intel/fsp_sandybridge/northbridge.h>
|
||||
#include <northbridge/intel/fsp_sandybridge/raminit.h>
|
||||
#include <southbridge/intel/fsp_i89xx/pch.h>
|
||||
#include <southbridge/intel/fsp_i89xx/gpio.h>
|
||||
#include <southbridge/intel/fsp_i89xx/me.h>
|
||||
#include <southbridge/intel/fsp_i89xx/romstage.h>
|
||||
#include <superio/winbond/wpcd376i/wpcd376i.h>
|
||||
#include <superio/intel/i8900/i8900.h>
|
||||
#include "gpio.h"
|
||||
|
||||
#define SIO_PORT 0x2e
|
||||
#define SERIAL_DEV PNP_DEV(SIO_PORT, 0x03)
|
||||
#define WDT_DEV PNP_DEV(SIO_PORT, 0x06)
|
||||
#define WDT_BASE_ADDR 0x600
|
||||
|
||||
/*
|
||||
* Get function disables - any changes here should match in devicetree
|
||||
* @param fd_mask
|
||||
* @param fd2_mask
|
||||
*/
|
||||
void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
|
||||
{
|
||||
*fd_mask |= PCH_DISABLE_ALWAYS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get LPC setting - enables various devices (KB, mouse, etc.)
|
||||
*/
|
||||
uint16_t get_lpc_setting(void)
|
||||
{
|
||||
/* Enable SuperIO (2E/4E) + COM1 & Keyboard controller */
|
||||
return CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN;
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done before fsp init
|
||||
*
|
||||
*/
|
||||
void early_mainboard_romstage_entry(void)
|
||||
{
|
||||
/* Early SuperIO setup - Using SIO Serial Port*/
|
||||
wpcd376i_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
i8900_enable_wdt(WDT_DEV, WDT_BASE_ADDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* /brief mainboard call for setup that needs to be done after fsp init
|
||||
*
|
||||
*/
|
||||
void late_mainboard_romstage_entry(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
|
||||
{
|
||||
/* No overrides needed */
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc.
|
||||
*/
|
||||
|
||||
#ifndef MAINBOARD_THERMAL_H
|
||||
#define MAINBOARD_THERMAL_H
|
||||
|
||||
/* Fan is OFF */
|
||||
#define FAN4_THRESHOLD_OFF 0
|
||||
#define FAN4_THRESHOLD_ON 0
|
||||
#define FAN4_PWM 0x00
|
||||
|
||||
/* Fan is at LOW speed */
|
||||
#define FAN3_THRESHOLD_OFF 48
|
||||
#define FAN3_THRESHOLD_ON 55
|
||||
#define FAN3_PWM 0x40
|
||||
|
||||
/* Fan is at MEDIUM speed */
|
||||
#define FAN2_THRESHOLD_OFF 52
|
||||
#define FAN2_THRESHOLD_ON 64
|
||||
#define FAN2_PWM 0x80
|
||||
|
||||
/* Fan is at HIGH speed */
|
||||
#define FAN1_THRESHOLD_OFF 60
|
||||
#define FAN1_THRESHOLD_ON 68
|
||||
#define FAN1_PWM 0xb0
|
||||
|
||||
/* Fan is at FULL speed */
|
||||
#define FAN0_THRESHOLD_OFF 66
|
||||
#define FAN0_THRESHOLD_ON 78
|
||||
#define FAN0_PWM 0xff
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 100
|
||||
|
||||
/* Temperature which OS will throttle CPU */
|
||||
#define PASSIVE_TEMPERATURE 90
|
||||
|
||||
/* Tj_max value for calculating PECI CPU temperature */
|
||||
#define MAX_TEMPERATURE 100
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue