soc/amd/mendocino: Set up SoC-specific XHCI defines

Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI.

BUG=b:186792595
TEST=builds

Change-Id: I16c789ff673c26ded84e4d46ab6dc743f33c5bb7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67938
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/mendocino/Kconfig

@@ -74,6 +74,7 @@ config SOC_AMD_REMBRANDT_BASE
 	select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_UART
 	select SOC_AMD_COMMON_BLOCK_UCODE
+	select SOC_AMD_COMMON_BLOCK_XHCI
 	select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB
 	select SOC_AMD_COMMON_FSP_DMI_TABLES
 	select SOC_AMD_COMMON_FSP_PCI

src/soc/amd/mendocino/include/soc/xhci.h

@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_MENDOCINO_XHCI_H
+#define AMD_MENDOCINO_XHCI_H
+
+#define SOC_XHCI_0 DEV_PTR(xhci_0)
+#define SOC_XHCI_1 DEV_PTR(xhci_1)
+#define SOC_XHCI_2 DEV_PTR(xhci_2)
+#define SOC_XHCI_3 NULL
+#define SOC_XHCI_4 NULL
+#define SOC_XHCI_5 NULL
+#define SOC_XHCI_6 NULL
+#define SOC_XHCI_7 NULL
+
+#endif /* AMD_MENDOCINO_XHCI_H */