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mb/intel/tglrvp: Enable D3HotEnable and D3ColdEnable for tglrvp 

This explicitly enables both of TCSS D3HotEnable and D3ColdEnable
from tglrvp devicetree.cb setting.

BUG=🅱️146624360
TEST=Built and booted on tglrvp.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3b77fe15bd67e513f193f704030a98241e058437
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
John Zhao 2020-05-19 20:21:00 -07:00 committed by Patrick Georgi
parent 8aac881fe8
commit 3c8cb24fc3
2 changed files with 8 additions and 0 deletions
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4
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -109,6 +109,10 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
# TCSS USB3
register "TcssAuxOri" = "0"

4
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -105,6 +105,10 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoPci,
}"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
# TCSS USB3
register "TcssAuxOri" = "0"