mainboard/lenovo/{t430s,t420s,t520,t530,x220}: Add TPM 1.2 mainboard support

Every Lenovo Thinkpad includes a Trusted Platform Module, so we can enable
it for the sandy-/ivybridge platforms.

Change-Id: Icda443ba88c2a49a0033014ce7710dd607fa15dc
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/10411
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Philipp Deppenwiese 2015-06-03 23:09:36 +02:00 committed by Patrick Georgi
parent 09705ab724
commit 3d02b9c79e
15 changed files with 65 additions and 0 deletions

View File

@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select SANDYBRIDGE_LVDS
select MAINBOARD_HAS_LPC_TPM
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE

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@ -112,6 +112,10 @@ chip northbridge/intel/sandybridge
register "dock_event_enable" = "0x01"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62

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@ -53,6 +53,14 @@ DefinitionBlock(
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

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@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select IVYBRIDGE_LVDS
select ENABLE_VMX
select MAINBOARD_HAS_LPC_TPM
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE

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@ -116,6 +116,10 @@ chip northbridge/intel/sandybridge
register "dock_event_enable" = "0x01"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62

View File

@ -53,6 +53,14 @@ DefinitionBlock(
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

View File

@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select SANDYBRIDGE_LVDS
select MAINBOARD_HAS_LPC_TPM
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE

View File

@ -93,6 +93,10 @@ chip northbridge/intel/sandybridge
register "dock_event_enable" = "0x01"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62

View File

@ -52,6 +52,14 @@ DefinitionBlock(
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

View File

@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select IVYBRIDGE_LVDS
select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init
select ENABLE_VMX
select MAINBOARD_HAS_LPC_TPM
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE

View File

@ -98,6 +98,10 @@ chip northbridge/intel/sandybridge
register "dock_event_enable" = "0x01"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62

View File

@ -52,6 +52,14 @@ DefinitionBlock(
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}

View File

@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
select SANDYBRIDGE_LVDS
select DRIVERS_RICOH_RCE822
select MAINBOARD_HAS_LPC_TPM
# Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE

View File

@ -126,6 +126,10 @@ chip northbridge/intel/sandybridge
register "dock_event_enable" = "0x01"
end
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/lenovo/h8
device pnp ff.2 on # dummy
io 0x60 = 0x62

View File

@ -52,6 +52,14 @@ DefinitionBlock(
}
}
/*
* LPC Trusted Platform Module
*/
Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/tpm/acpi/tpm.asl>
}
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
}