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AGESA: Drop CONFIG_CBB and CONFIG_CDB 

Static values, copy paste from multi-node fam15 code.

Add header that shall have declarations of functions
common to different families factored out.

Change-Id: I07bc046c74280f49e46793c119d36b87b8789949
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2019-01-10 09:05:30 +02:00
parent bbd237702a
commit 3d3152eec7
13 changed files with 45 additions and 52 deletions
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8
src/cpu/amd/agesa/family12/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 48
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000

8
src/cpu/amd/agesa/family14/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 36
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x80000

8
src/cpu/amd/agesa/family15tn/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 48
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x100000

8
src/cpu/amd/agesa/family16kb/Kconfig
View File

@ -23,14 +23,6 @@ config CPU_ADDR_BITS
int
default 40
config CBB
hex
default 0x0
config CDB
hex
default 0x18
config XIP_ROM_SIZE
hex
default 0x100000

2
src/northbridge/amd/agesa/family12/amdfam12_conf.c
View File

@ -27,7 +27,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
struct device *dev;
struct dram_base_mask_t d;
#if defined(__PRE_RAM__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
dev = PCI_DEV(0, DEV_CDB, 1);
#else
dev = __f1_dev[0];
#endif // defined(__PRE_RAM__)

5
src/northbridge/amd/agesa/family12/northbridge.c
View File

@ -33,6 +33,7 @@
#include "sb_cimx.h"
#include <northbridge/amd/agesa/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@ -46,7 +47,7 @@ static unsigned fx_devs = 0;
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -89,7 +90,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam12_nodeid(struct device *dev)
{
printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__);
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
#include "amdfam12_conf.c"

2
src/northbridge/amd/agesa/family14/amdfam14_conf.c
View File

@ -27,7 +27,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
struct device *dev;
struct dram_base_mask_t d;
#if defined(__PRE_RAM__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
dev = PCI_DEV(0, DEV_CDB, 1);
#else
dev = __f1_dev[0];
#endif // defined(__PRE_RAM__)

5
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -29,6 +29,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <sb_cimx.h>
@ -43,7 +44,7 @@ static unsigned fx_devs = 0;
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -85,7 +86,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam14_nodeid(struct device *dev)
{
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
#include "amdfam14_conf.c"

11
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -34,6 +34,7 @@
#include <Porting.h>
#include <Options.h>
#include <Topology.h>
#include <northbridge/amd/agesa/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@ -99,7 +100,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -142,7 +143,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam15_nodeid(struct device *dev)
{
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@ -818,9 +819,9 @@ static void cpu_bus_scan(struct device *dev)
int siblings = 0;
unsigned int family;
dev_mc = pcidev_on_root(CONFIG_CDB, 0);
dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die("");
}
sysconf_init(dev_mc);
@ -843,7 +844,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn;
struct bus *pbus;
devn = CONFIG_CDB + i;
devn = DEV_CDB + i;
pbus = dev_mc->bus;
/* Find the cpu's pci device */

11
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -33,6 +33,7 @@
#include <AGESA.h>
#include <Options.h>
#include <Topology.h>
#include <northbridge/amd/agesa/nb_common.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@ -98,7 +99,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi
static struct device *get_node_pci(u32 nodeid, u32 fn)
{
return pcidev_on_root(CONFIG_CDB + nodeid, fn);
return pcidev_on_root(DEV_CDB + nodeid, fn);
}
static void get_fx_devs(void)
@ -141,7 +142,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam16_nodeid(struct device *dev)
{
return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
return (dev->path.pci.devfn >> 3) - DEV_CDB;
}
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
@ -843,9 +844,9 @@ static void cpu_bus_scan(struct device *dev)
int siblings = 0;
unsigned int family;
dev_mc = pcidev_on_root(CONFIG_CDB, 0);
dev_mc = pcidev_on_root(DEV_CDB, 0);
if (!dev_mc) {
printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB);
die("");
}
sysconf_init(dev_mc);
@ -868,7 +869,7 @@ static void cpu_bus_scan(struct device *dev)
unsigned devn;
struct bus *pbus;
devn = CONFIG_CDB + i;
devn = DEV_CDB + i;
pbus = dev_mc->bus;
/* Find the cpu's pci device */

19
src/northbridge/amd/agesa/nb_common.h Normal file
View File

@ -0,0 +1,19 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __AMD_NB_COMMON_H__
#define __AMD_NB_COMMON_H__
#define DEV_CDB 0x18
#endif

5
src/southbridge/amd/cimx/sb800/reset.c
View File

@ -23,7 +23,8 @@
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#define DEV_CDB 0x18
#define NODE_PCI(x, fn) (((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn)))
void cf9_reset_prepare(void)
{
@ -32,7 +33,7 @@ void cf9_reset_prepare(void)
pci_devfn_t dev;
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1;
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);

5
src/southbridge/amd/cimx/sb900/reset.c
View File

@ -23,7 +23,8 @@
#define HT_INIT_CONTROL 0x6C
#define HTIC_BIOSR_Detect (1<<5)
#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#define DEV_CDB 0x18
#define NODE_PCI(x, fn) (((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn)))
void cf9_reset_prepare(void)
{
@ -32,7 +33,7 @@ void cf9_reset_prepare(void)
pci_devfn_t dev;
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1;
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);